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  • 1
    Publication Date: 2011-08-19
    Description: Barrier height enhancement of an InP-based p(+)n-Ga(0.47)In(0.53)As Schottky diode grown by MBE has been demonstrated for infra-red photodetector applications. A barrier height of 0.35 eV for n-Ga(0.47)In(0.53)As Schottky barrier diodes, was increased to the effective barrier height of 0.55 eV, with a p(+)-Ga(0.47)In(0.53)As surface layer of 30 nm thick. The results show a reverse leakage current density of 0.0015 A/sq cm and a junction capacitance of 0.3 pF, which are comparable to those of p-Ga(0.47)In(0.53)As Schottky-barrier diodes at a reverse bias voltage of 5 V.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: Electronics Letters (ISSN 0013-5194); 24; 687-689
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  • 2
    Publication Date: 2011-08-16
    Description: The paper outlines the design, principles of operation, and calibration of a five-IC network intended to give a rapid, precise, and automatic determination of the flatband voltage of MOS capacitors. The basic principle of measurement is to compare the analog output voltage of a capacitance meter - which is directly proportional to the capacitance being measured - with a preset or dialed-in voltage proportional to the calculated flatband capacitance by means of a comparator circuit. The bias to the MOS capacitor supplied through the capacitance meter is provided by a ramp voltage going from a negative toward a positive voltage level and vice versa. The network employs two monostable multivibrators for reading and recording the flatband voltage and for resetting the initial conditions and restarting the ramp. The flatband voltage can be held and read on a digital voltmeter.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: Review of Scientific Instruments; 47; May 1976
    Format: text
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  • 3
    Publication Date: 2019-06-27
    Description: The model for field-time-dependent breakdown in the gate oxide of MOS devices is extended and verified with experimental data. The model permits accelerated tests at high fields which can be used to predict gate-oxide breakdowns at much longer times at normal operating fields.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: Solid-State Electronics; 22; Nov. 197
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  • 4
    Publication Date: 2019-06-27
    Description: The statistical nature of time-dependent dielectric breakdown characteristics in MOS capacitors was evidenced by testing large numbers of capacitors fabricated on single wafers. A multipoint probe and automatic electronic visual display technique are introduced that will yield statistical results which are necessary for the investigation of temperature, electric field, thermal annealing, and radiation effects in the breakdown characteristics, and an interpretation of the physical mechanisms involved. It is shown that capacitors of area greater than 0.002 sq cm may yield worst-case results, and that a multipoint probe of capacitors of smaller sizes can be used to obtain a profile of nonuniformities in the SiO2 films.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: Microelectronics and Reliability; 13; June 197
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  • 5
    Publication Date: 2019-06-27
    Description: A new procedure for measuring effective defect density takes time-dependent primary dielectric breakdown in MOS devices into account. A time-varying breakdown probability is obtained by applying a constant field stress to a statistically sufficient number of MOS capacitors. Effective defects are assumed distributed randomly in two dimensions, hence indistinguishable. The effective defect density is found to vary with oxide thickness; tentative explanations are ventured to account for this (interfacial tensile stress, ion patching enhanced by local trapping, breakdown in the form of filamentary discharges with release of stored electrostatic energy).
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: IEEE Transactions on Electron Devices; ED-23; May 1976
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  • 6
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    In:  Other Sources
    Publication Date: 2019-06-27
    Description: A general model for time-dependent breakdown in metal-oxide-silicon (MOS) structures is developed and related to experimental measurements on samples deliberately contaminated with Na. A statistical method is used for measuring the breakdown probability as a function of log time and applied field. It is shown that three time regions of breakdown can be explained respectively in terms of silicon surface defects, ion emission from the metal interface, and lateral ion diffusion at the silicon interface.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: Solid-State Electronics; 19; Mar. 197
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  • 7
    Publication Date: 2019-06-27
    Description: Implantation of Ne ions was chosen as a means of introducing a uniformly distributed quantitatively controllable and reproducible amount of microdefects at the silicon surface. Each wafer was ion-implanted on one half of its surface, the other half remaining as a control. Seven implant fluences from 1 trillion to 5 by 10 to the 14th power Ne ions/sq cm were used. The fluences, as well as the concentrations of defects expanded by the subsequent gate oxidation, were correlated with seven different MOS parameters. For implant fluences of 10 to the 14th power per sq cm and above, increasing stacking-fault densities were found. The oxide defect density associated with time-dependent breakdown increased significantly with Ne dose. The presence of oxidation-expanded defects drastically increases the surface-generation velocity and decreases the bulk lifetime. Slight increases in flatband voltage and surface-state density occurred only for the wafers having the greatest defect concentrations. Oxidation of a P-containing damaged silicon surface results in a greater pileup of P at the surface than occurs for the oxidation of a similar but undamaged surface. It appears that the expanding defects restrain the diffusion of P inward from the surface.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: Journal of Applied Physics; 48; Nov. 197
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  • 8
    Publication Date: 2019-07-13
    Description: A 5 nm-thick SiO2 gate was grown on an Si(p+)/Si(0.8)Ge(0.2) modulation-doped heterostructure at 26 C with an oxygen plasma generated by a multipolar electron cyclotron resonance source. The ultrathin oxide has breakdown field above 12 MV/cm and fixed charge density about 3 x 10 exp 10/sq cm. Leakage current as low as 1/micro-A was obtained with the gate biased at 4 V. The MISFET with 0.25 x 25 sq m gate shows maximum drain current of 41.6 mA/mm and peak transconductance of 21 mS/mm.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: Electronics Letters (ISSN 0013-5194); 29; 3; p. 277, 278.
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  • 9
    Publication Date: 2019-07-13
    Description: A quantitative model for MOS breakdown is derived and correlated with experiments. The data were obtained by enhancing the effect of ion emission on breakdown through controlled ion-implantation damage prior to gate oxidation in an otherwise normal and clean MOS process
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: Reliability physics 1978; Apr 18, 1978 - Apr 20, 1978; San Diego, CA
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