Publication Date:
2019-06-28
Description:
The architecture and VLSI design of a new massively parallel processing array chip are described. The BLITZEN processing element array chip, which contains 1.1 million transistors, serves as the basis for a highly integrated, miniaturized, high-performance, massively parallel machine that is currently under development. Each processing element has 1K bits of static RAM and performs bit-serial processing with functional elements for arithmetic, logic, and shifting.
Keywords:
COMPUTER SYSTEMS
Type:
NASA, Goddard Space Flight Center, The 2nd Symposium on the Frontiers of Massively Parallel Computations; p 399-406
Format:
application/pdf
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