Publication Date:
2019-06-27
Description:
A binary coded input signal is converted to a binary coded decimal signal having N decades by employing N four bit shift registers. The bits of the input signal are sequentially supplied, in order, to the least significant position of the register for the units decade, with the most significant bit of the input signal being applied to the units register first. Each of the registers includes a right shift-parallel load mode control input terminal. In response to the sum of the values stored in each register and the binary value 0011 being less than the binary value 1000, the mode control input terminal is activated to shift the register contents one bit to the right. In response to the sum being greater than 1000, the mode control input terminal is activated to load the sum into the register.
Keywords:
COMPUTER OPERATIONS AND HARDWARE
Format:
application/pdf
Permalink
