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  • 1
    Electronic Resource
    Electronic Resource
    Springer
    The journal of VLSI signal processing systems for signal, image, and video technology 15 (1997), S. 207-220 
    ISSN: 1573-109X
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract This paper addresses embedded multiprocessor implementation of iterative, real-time applications, such as digital signal and image processing, that are specified as dataflow graphs. Scheduling dataflow graphs on multiple processors involves assigning tasks to processors (processor assignment), ordering the execution of tasks within each processor (task ordering), and determining when each task must commence execution. We consider three scheduling strategies: fully-static, self-timed and ordered transactions, all of which perform the assignment and ordering steps at compile time. Run time costs are small for the fully-static strategy; however it is not robust with respect to changes or uncertainty in task execution times. The self-timed approach is tolerant of variations in task execution times, but pays the penalty of high run time costs, because processors need to explicitly synchronize whenever they communicate. The ordered transactions approach lies between the fully-static and self-timed strategies; in this approach the order in which processors communicate is determined at compile time and enforced at run time. The ordered transactions strategy retains some of the flexibility of self-timed schedules and at the same time has lower run time costs than the self-timed approach. In this paper we determine an order of processor transactions that is nearly optimal given information about task execution times at compile time, and for a given processor assignment and task ordering. The criterion for optimality is the average throughput achieved by the schedule. Our main result is that it is possible to choose a transaction order such that the resulting ordered transactions schedule incurs no performance penalty compared to the more flexible self-timed strategy, even when the higher run time costs implied by the self-timed strategy are ignored.
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  • 2
    Electronic Resource
    Electronic Resource
    Springer
    The journal of VLSI signal processing systems for signal, image, and video technology 15 (1997), S. 127-144 
    ISSN: 1573-109X
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract This paper relates to system-level design of signal processing systems, which are often heterogeneous in implementation technologies and design styles. The heterogeneous approach, by combining small, specialized models of computation, achieves generality and also lends itself to automatic synthesis and formal verification. Key to the heterogeneous approach is to define interaction semantics that resolve the ambiguities when different models of computation are brought together. For this purpose, we introduce a tagged signal model as a formal framework within which the models of computation can be precisely described and unambiguously differentiated, and their interactions can be understood. In this paper, we will focus on the interaction between dataflow models, which have partially ordered events, and discrete-event models, with their notion of time that usually defines a total order of events. A variety of interaction semantics, mainly in handling the different notions of time in the two models, are explored to illustrate the subtleties involved. An implementation based on the Ptolemy system from U.C. Berkeley is described and critiqued.
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  • 3
    Electronic Resource
    Electronic Resource
    Springer
    The journal of VLSI signal processing systems for signal, image, and video technology 14 (1996), S. 157-169 
    ISSN: 1573-109X
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract The system-level design problem spans a large design space. Typically, the designer needs to explore possible target architectures, experiment with different tools, and work with a range of constrains and optimization criteria. This design process is quite complex and involves considerable bookkeeping and management, in addition to sophisticated design tools. We believe that managing the design process is an important (although often neglected) part of system-level design. The contribution of this paper is in two parts. First, we present a framework for systematically managing the design process. Secondly, we illustrate how this framework can be used to manage a system-level design environment that consists of a suite of sophisticated hardware and software design tools. We begin by identifying some of the desirable features of system-level design methodology management. A candidate framework that manifests these features is presented. Complex design flows with iterative and conditional behavior can be specified within the framework. The framework also supports automated scheduling of tools in a well-defined design flow. It has been implemented as the DMM domain in Ptolemy. In the second part of the paper, we describe a case study that we have developed within this framework. The case study, called the Design Assistant, is a complete hardware-software codesign environment. It encapsulates various codesign tools for specification, partitioning, and synthesis; their interplay can be managed efficiently by the design methodology management framework.
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  • 4
    Electronic Resource
    Electronic Resource
    Springer
    The journal of VLSI signal processing systems for signal, image, and video technology 21 (1999), S. 151-166 
    ISSN: 1573-109X
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract The implementation of software for embedded digital signal processing (DSP) applications is an extremely complex process. The complexity arises from escalating functionality in the applications; intense time-to-market pressures; and stringent cost, power and speed constraints. To help cope with such complexity, DSP system designers have increasingly been employing high-level, graphical design environments in which system specification is based on hierarchical dataflow graphs. Consequently, a significant industry has emerged for the development of data-flow-based DSP design environments. Leading products in this industry include SPW from Cadence, COSSAP from Synopsys, ADS from Hewlett Packard, and DSP Station from Mentor Graphics. This paper reviews a set of algorithms for compiling dataflow programs for embedded DSP applications into efficient implementations on programmable digital signal processors. The algorithms focus primarily on the minimization of code size, and the minimization of the memory required for the buffers that implement the communication channels in the input dataflow graph. These are critical problems because programmable digital signal processors have very limited amounts of on-chip memory, and the speed, power, and cost penalties for using off-chip memory are often prohibitively high for embedded applications. Furthermore, memory demands of applications are increasing at a significantly higher rate than the rate of increase in on-chip memory capacity offered by improved integrated circuit technology.
    Type of Medium: Electronic Resource
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  • 5
    Electronic Resource
    Electronic Resource
    Springer
    The journal of VLSI signal processing systems for signal, image, and video technology 6 (1993), S. 271-288 
    ISSN: 1573-109X
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Synchronous dataflow (SDF) has been used to synthesize code for programmable DSPs to implement multirate and block oriented signal processing systems. However, with large block sizes, or significant sample rate changes, program memory consumption becomes a critical problem. This article develops a compile-time algorithm for scheduling SDF graphs to exploit opportunities for looping—the successive reoccurrence of identical firing patterns. Because SDF graphs allow actors to produce or consume an arbitrary number of tokens on each input or output, complicated control flow may result. Yet in static scheduling, it is desirable to execute sections of the target code within loop constructs, such as “do-while,” to reduce program-memory requirements. To do this, the SDF graph is hierarchically clustered, carefully avoiding deadlock while exposing looping opportunities. Results of applying these loop-extraction algorithms show orders of magnitude of compaction for target program code space on programmable DSPs compared to in-line code.
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  • 6
    Electronic Resource
    Electronic Resource
    Springer
    The journal of VLSI signal processing systems for signal, image, and video technology 9 (1995), S. 7-21 
    ISSN: 1573-109X
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Ptolemy is an environment for simulation, prototyping, and software synthesis for heterogeneous systems. It uses modern object-oriented software technology (in C++) to model each subsystem in a natural and efficient manner, and to integrate these subsystems into a whole. The objectives of Ptolemy encompass practically all aspects of designing signal processing and communications systems, ranging from algorithms and communication strategies, through simulation, hardware and software design, parallel computing, and generation of real-time prototypes. In this paper we will introduce the software synthesis aspects of the Ptolemy system. The environment presented here is both modular and extensible. Ptolemy allows the user to choose among various single- or multiple-processor schedulers.
    Type of Medium: Electronic Resource
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  • 7
    Electronic Resource
    Electronic Resource
    Springer
    Annals of software engineering 7 (1999), S. 25-45 
    ISSN: 1573-7489
    Source: Springer Online Journal Archives 1860-2000
    Topics: Computer Science
    Notes: Abstract We give a formal framework for studying real-time discrete-event systems. It describes concurrent processes as sets of possible behaviors. Compositions of processes are processes with behaviors in the intersection of the behaviors of the component processes. The interaction between processes is through signals, which are collections of events. Each event is a value-tag pair, where the tags denote time. Zeno conditions are defined and methods are given for avoiding them. Strict causality ensures determinacy under certain technical conditions, and delta-causality ensures the absence of Zeno conditions.
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  • 8
    ISSN: 1572-8080
    Keywords: Dataflow programming ; synchronous dataflow ; memory management ; multirate signal processing algorithms ; SDF compiler ; on-chip memory ; clustering ; minimum cuts ; dynamic programming
    Source: Springer Online Journal Archives 1860-2000
    Topics: Computer Science
    Notes: Abstract Dataflow has proven to be an attractive computational model for graphical DSP design environments that support the automatic conversion of hierarchical signal flow diagrams into implementations on programmable processors. The synchronous dataflow (SDF) model is particularly well-suited to dataflow-based graphical programming because its restricted semantics offer strong formal properties and significant compile-time predictability, while capturing the behavior of a large class of important signal processing applications. When synthesizing software for embedded signal processing applications, critical constraints arise due to the limited amounts of memory. In this paper, we propose a solution to the problem of jointly optimizing the code and data size when converting SDF programs into software implementations. We consider two approaches. The first is a customization to acyclic graphs of a bottom-up technique, called pairwise grouping of adjacent nodes (PGAN), that was proposed earlier for general SDF graphs. We show that our customization to acyclic graphs significantly reduces the complexity of the general PGAN algorithm, and we present a formal study of our modified PGAN technique that rigorously establishes its optimality for a certain class of applications. The second approach that we consider is a top-down technique, based on a generalized minimum-cut operation, that was introduced recently in [14]. We present the results of an extensive experimental investigation on the performance of our modified PGAN technique and the top-down approach and on the trade-offs between them. Based on these results, we conclude that these two techniques complement each other, and thus, they should both be incorporated into SDF-based software implementation environments in which the minimization of memory requirements is important. We have implemented these algorithms in the Ptolemy software environment [5] at UC Berkeley.
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  • 9
    Electronic Resource
    Electronic Resource
    Springer
    Design automation for embedded systems 2 (1997), S. 125-163 
    ISSN: 1572-8080
    Source: Springer Online Journal Archives 1860-2000
    Topics: Computer Science
    Notes: Abstract In system-level design, applications are represented as task graphs where tasks (called nodes) have moderate to large granularity and each node has several implementation options differing in area and execution time. We define the extended partitioning problem as the joint determination of the mapping (hardware or software), the implementation option (called implementation bin), as well as the schedule, for each node, so that the overall area allocated to nodes in hardware is minimum and a deadline constraint is met. This problem is considerably harder (and richer) than the traditional binary partitioning problem that determines just the best mapping and schedule. Both binary and extended partitioning problems are constrained optimization problems and are NP-hard. We first present an efficient(O(N 2)) heuristic, called GCLP, to solve the binary partitioning problem. The heuristic reduces the greediness associated with traditional list-scheduling algorithms by formulating a global measure, called global criticality (GC). The GC measure also permits an adaptive selection of the optimization objective at each step of the algorithm; since the optimization problem is constrained by a deadline, either area or time is optimized at a given step based on the value of GC. The selected objective is used to determine the mapping of nodes that are “normal”, i.e. nodes that do not exhibit affinity for a particular mapping. To account for nodes that are not “normal”, we define “extremities” and “repellers”. Extremities consume disproportionate amounts of resources in hardware and software. Repellers are inherently unsuitable to either hardware or software based on certain structural properties. The mapping of extremities and repellers is determined jointly by GC and their local preference. We then present an efficient ( O(N 3 + N 2 B), for N nodes and B bins per node) heuristic for extended partitioning, called MIBS, that alternately uses GCLP and an implementation-bin selection procedure. The implementation-bin selection procedure chooses, for a node with already determined mapping, an implementation bin that maximizes the area-reduction gradient of as-yet unmapped nodes. Solutions generated by both heuristics are shown to be reasonably close to optimal. Extended partitioning generates considerably smaller overall hardware as compared to binary partitioning.
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  • 10
    Electronic Resource
    Electronic Resource
    Springer
    Formal methods in system design 11 (1997), S. 41-70 
    ISSN: 1572-8102
    Keywords: dataflow programming ; synchronous dataflow ; memory management ; multirate signal processing algorithms ; SDF compiler ; on-chip memory ; minimum cuts ; dynamic programming
    Source: Springer Online Journal Archives 1860-2000
    Topics: Computer Science
    Notes: Abstract In this paper, we formally develop techniques that minimize the memory requirements of a target program when synthesizing software from dataflow descriptions of multirate signal processing algorithms. The dataflow programming model that we consider is the synchronous dataflow (SDF) model [21], which has been used heavily in DSP design environments over the past several years. We first focus on the restricted class of well-ordered SDF graphs. We show that while extremely efficient techniques exist for constructing minimum code size schedules for well-ordered graphs, the number of distinct minimum code size schedules increases combinatorially with the number of vertices in the input SDF graph, and these different schedules can have vastly different data memory requirements. We develop a dynamic programming algorithm that computes the schedule that minimizes the data memory requirement from among the schedules that minimize code size, and we show that the time complexity of this algorithm is cubic in the number of vertices in the given well-ordered SDF graph. We present several extensions to this dynamic programming technique to more general scheduling problems, and we present a heuristic that often computes near-optimal schedules with quadratic time complexity. We then show that finding optimal solutions for arbitrary acyclic graphs is NP-complete, and present heuristic techniques that jointly minimize code and data size requirements. We present a practical example and simulation data that demonstrate the effectiveness of these techniques.
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