AIP Digital Archive
GaAs metal-semiconductor field-effect transistors (MESFETs) and other integrated-circuit elements were characterized by including extensive process test sites on wafers with digital logic and memory circuits. A self-aligned, refractory-gate enhancement/depletion (E/D) process was employed which included 47SiF+ channel and source/drain implants, capless arsenic overpressure furnace annealing, WSi0.11 gate metal with in situ sputter cleaning, Ni-Au-Ge ohmic contacts, Si3N4 or SiO2 insulation, and Ni-Au wiring. On-water threshold voltage standard deviations as low as 31 mV for 1-μm E-FETs and 49 mV for 1-μm D-FETs were measured using 51-mm standard semi-insulating liquid-encapsulated Czochralski GaAs substrates. Threshold voltage control from wafer to wafer was of order 100 mV. Schottky diode barrier height was about 0.73 eV with an ideality of 1.2, although small self-aligned Schottky gates often showed excess conduction believed to occur at the gate edges. FET square-law coefficient, subthreshold leakage, gate capacitance, backgating, contact resistance, and wiring and insulation characteristics were also measured and found satisfactory. Fully functional 1-μm gate E/D MESFET circuits including a 4×4 bit multiplier, a 4×4 crosspoint switch, a 448-bit static RAM, and an integrated photodiode amplifier were demonstrated.
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