In order to investigate the effects of interface and bulk properties of gate insulator on the threshold voltage (V th ) and the gate-bias induced instability of hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs), four kinds of TFT structures were fabricated with SiNx and SiOx insulators stacked to make different combinations of the bulk and interface in the gate-dielectric layers. It was found that the V th and the stability are independently controlled by tuning stoichiometry and thickness of the SiOx insertion layer between a-Si:H and SiNx. In TFTs with SiO x insertion layer of 50 nm thickness, on increasing oxygen/silicon (O/Si = x) ratio from 1.7 to 1.9, V th increased from 0 V to 9 V. In these TFTs with a relatively thick SiOx insertion layer, positive V th shift with negative bias stress was observed, confirmed to be due to defect creation in a-Si:H with the thermalization barrier energy of 0.83 eV. On reducing the thickness of the SiOx insertion layer down to approximately 1 nm, thin enough for hole injection through SiOx by tunneling effect, stable operation was obtained while keeping the high V th value under negative stress bias. These results are consistently explained as follows: (1) the high value for V th is caused by the dipole generated at the interface between a-Si:H and SiOx; and (2) two causes for V th shift, charge injection to the gate insulator and defect creation in a-Si:H, are mutually related to each other through the “effective bias stress,” V bs eff = V bs – ΔV fb (V bs : applied bias stress and ΔV fb : flat band voltage shift due to the charge injection). It was experimentally confirmed that there should be an optimum thickness of SiO x insertion layer of approximately 1 nm with stable high V th , where enhanced injection increases ΔV fb , reduces V bs eff to reduce defect creation, and totally minimizes V th shift.