Springer Online Journal Archives 1860-2000
Abstract Metal/insulator/semiconductor junctions are prepared on degeneratep-type InAs substrates with hole concentrations ranging from 2.3×1017 cm−3 to 2.7×1018 cm−3. The low work function of the top metal Yb, Al, or Au and charged interface states influence a two-dimensional (2D) electron inversion layer at the InAs surface. The insulator barrier that is formed by thermal oxidation is designed sufficiently thin, so that the bias voltage applied at the metal electrode mainly drops across the depletion layer separating the electron channel from the bulk. The current-voltage (I–V) characteristics exhibit strong negative differential conductance due to interband, tunneling from the 2D subband into the 3D valence band with peak-to-valley current ratios up to 3.1, 18, and 32 at 300 K, 77 K, and 4.2 K, respectively. In agreement with a theoretical model based on coherentelastic tunneling, the form of the I–V curves resembles those of double-barrier resonant tunnel devices rather than those of 3D Esaki diodes. The series resistance is obtained from the saturation of the differential conductance dI/dV at high forward bias and from the shift of structures in d2 I/dV 2 arising from phonon assisted tunneling.
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