ISSN:
1573-0727
Keywords:
concurrent error detection
;
on-line testing
;
built-in-self-test
;
parity-preserving signature analyzer
Source:
Springer Online Journal Archives 1860-2000
Topics:
Electrical Engineering, Measurement and Control Technology
Notes:
Abstract In this paper a joint implementation of a parity preserving multi-input signature analyzer (PMISA) and a parity checker is described. The PMISA simultaneously can be used for concurrent checking and for testing of digital circuits. In the case of concurrent checking errors are detected by their erroneous parity. If a circuit is tested errors are detected either by their erroneous parity or by the erroneous signature of the PMISA. A possible scan-mode of the PMISA allows its application in a scan path with parity-encoded inputs and outputs of the combinational modules which are driven by register sets. In normal operation mode all the registers of the PMISA can be utilized as functional registers of the combinational circuit.
Type of Medium:
Electronic Resource
URL:
http://dx.doi.org/10.1007/BF02341822
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