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  • 1
    Publication Date: 2019-07-13
    Description: Recent commercial developments in multicore processors (e.g. Tilera, Clearspeed, HyperX) have provided an option for high performance embedded computing that rivals the performance attainable with FPGA-based reconfigurable computing architectures. Furthermore, these processors offer more straightforward and streamlined application development by allowing the use of conventional programming languages and software tools in lieu of hardware design languages such as VHDL and Verilog. With these advantages, multicore processors can significantly enhance the capabilities of future robotic space missions. This paper will discuss these benefits, along with onboard processing applications where multicore processing can offer advantages over existing or competing approaches. This paper will also discuss the key artchitecural features of current commercial multicore processors. In comparison to the current art, the features and advancements necessary for spaceflight multicore processors will be identified. These include power reduction, radiation hardening, inherent fault tolerance, and support for common spacecraft bus interfaces. Lastly, this paper will explore how multicore processors might evolve with advances in electronics technology and how avionics architectures might evolve once multicore processors are inserted into NASA robotic spacecraft.
    Keywords: Cybernetics, Artificial Intelligence and Robotics
    Type: InfoTech@Aerospace 2011; Mar 28, 2011 - Mar 30, 2011; Saint Louis, MO; United States
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  • 2
    Publication Date: 2019-07-13
    Description: The High Performance Spaceflight Computing (HPSC) multi-core processor Chiplet will provide a nearly two orders-of-magnitude improvement above the current state of the art for spaceflight processors, while also providing an unprecedented flexibility to tailor performance, power consumption, and fault tolerance to meet widely varying mission needs. These advancements will provide game changing improvements in computing performance, power efficiency, and flexibility, which will significantly improve the onboard processing capabilities of future NASA and Air Force space missions. HPSC is funded by NASA's Space Technology Mission Directorate (STMD), Science Mission Directorate (SMD), and the United States Air Force. The HPSC project is managed by Jet Propulsion Laboratory, and the HPSC contract is managed by NASA Goddard Space Flight Center (GSFC). Within the HPSC project, Boeing is under contract to NASA to develop prototype Chiplets, system software, and evaluation boards. As another development within the project, NASA Goddard Space Flight Center (GSFC) and the Jet Propulsion Laboratory (JPL) are developing middleware that will simplify application development for HPSC-based onboard processors.
    Keywords: Computer Systems; Astronautics (General)
    Type: GSFC-E-DAA-TN62651 , Radiation Hardened Electronics Technology Conference (RHET) 2018; Nov 05, 2018 - Nov 07, 2018; Phoenix, AZ; United States
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  • 3
    Publication Date: 2019-07-13
    Description: NASA Goddard Spaceflight Center (GSFC) employs standard avionics hardware and software architectures. Hardware architectures include GMSA (Goddard Modular Smallsat Architecture), MUSTANG (Modular Unified Space Technology Avionics for Next Generation), SpaceCube. The spaceflight software architecture is based on cFS (Core Flight System). Future driving requirements for avionics architectures include increase sensor data rates, increased onboard processing, autonomous applications, and distributed space missions. Architectural concepts that can meet these requirements include the use of the High Performance Spaceflight Computing (HPSC) Chiplet, employing hybrid computing architectures, and increasing network bandwidths.
    Keywords: Spacecraft Instrumentation and Astrionics
    Type: GSFC-E-DAA-TN57153 , Space Computing & Connected Enterprise Resiliency Conference (SCCERC 2018); Jun 04, 2018 - Jun 08, 2018; Bedford, MA; United States
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  • 4
    Publication Date: 2019-07-13
    Description: In this paper, a comparison between the effects of irradiating microelectronics with high energy electrons and Cobalt-60 gamma-rays is examined. Additionally, the effect of electron energy is also discussed. A variety of part types are investigated, including discrete bipolar transistors, hybrids, and junction field effect transistors
    Keywords: Space Radiation; Electronics and Electrical Engineering
    Type: LEGNEW-OLDGSFC-GSFC-LN-1174 , IEEE Nuclear and Space Radiation Effects Conference (NSREC); Jul 16, 2012 - Jul 20, 2012; Miami, FL; United States
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  • 5
    Publication Date: 2019-07-13
    Description: This presentation provides an overview of NASA GSFC, our onboard processing applications, the applicability heterogeneous processing to these applications, and necessary developments to enable heterogeneous processing to be infused into our missions.
    Keywords: Electronics and Electrical Engineering
    Type: GSFC-E-DAA-TN31919 , IEEE International Symposium on Field-Programmable Custom Computing Machines; May 01, 2016 - May 03, 2016; Washington, DC; United States
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  • 6
    Publication Date: 2019-07-19
    Description: Housekeeping systems are essential to health monitoring of spacecraft and instruments. Typically, sensors are distributed across various sub-systems and data is collected using components such as analog-to-digital converters, analog multiplexers and amplifiers. In most cases programmable devices are used to implement the data acquisition control and storage, and the interface to higher level systems. Such discrete implementations require additional size, weight, power and interconnect complexity versus an integrated circuit solution, as well as the qualification of multiple parts. Although commercial devices are readily available, they are not suitable for space applications due the radiation tolerance and qualification requirements. The Housekeeping System-o n-A-Chip (HKSOC) is a low power, radiation hardened integrated solution suitable for spacecraft and instrument control and data collection. A prototype has been designed and includes a wide variety of functions including a 16-channel analog front-end for driving and reading sensors, analog-to-digital and digital-to-analog converters, on-chip temperature sensor, power supply current sense circuits, general purpose comparators and amplifiers, a 32-bit processor, digital I/O, pulse-width modulation (PWM) generators, timers and I2C master and slave serial interfaces. In addition, the device can operate in a bypass mode where the processor is disabled and external logic is used to control the analog and mixed signal functions. The device is suitable for stand-alone or distributed systems where multiple chips can be deployed across different sub-systems as intelligent nodes with computing and processing capabilities.
    Keywords: Electronics and Electrical Engineering
    Type: GSFC.ABS.7497.2012 , 2013 IEEE Aerospace Conference; 209 Mar. 2013; Big Sky, MT; United States
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