ALBERT

Notes: The epitaxial silicon growth temperature has been reduced to as low as 250 °C by optimizing the ion bombardment condition in low-energy bias sputtering process. Independent and precise control of ion bombardment energy and ion flux density incident on a growing film surface is most essential to realize very low temperature epitaxy. It has been experimentally shown that the deficit in energy for epitaxial growth by reducing the substrate temperature is able to be compensated for by increasing the total energy dose on a film surface by low-energy ion bombardment. Increase in the impact energy of individual ions, however, results in the formation of high-density defects in the film. Therefore, the right direction to enhance the total energy deposition by ion bombardment is to increase the ion flux density while keeping the ion impact energy at an optimum value. As a result of such optimization, epitaxial growth of silicon has become possible at a temperature as low as 250 °C. The etch pit density in this low-temperature growth film is less than 3×103 cm−2, the detection limit of our experiments. The carbon and oxygen concentrations in a grown film as measured by secondary ion mass spectroscopy increase with the background pressure, and these impurity concentrations are correlated to the crystallinity of the film. From these observations, the profound effect of contamination on the reduction of silicon epitaxial temperature is demonstrated.

Notes: In order to clarify the origin of enhanced leakage currents observed in As+-implanted junctions annealed at a temperature as low as 450 °C [M. M. Oka, A. Nakada, K. Tomita, T. Shibata, T. Ohmi, and T. Nitta, Jpn. J. Appl. Phys. 34, 796 (1995)], two-step implantation/anneal experiments have been conducted and the spatial distribution of end-of-range defects has been investigated. As a result, it has been demonstrated that the residual damage in 450 °C annealed junctions is strongly influenced by the doping level of p-type silicon substrate. The defects were found deeply distributing in the substrate, i.e., about 350 nm below the silicon surface when the doping level was 2.5×1015 cm−3. The defect distribution further extends for higher boron doping levels. Taking these experimental results into account, As +-implanted n+p junctions were formed on substrates having varying doping levels. About two orders of magnitude reduction in the leakage current was observed with decrease in the substrate boron concentration from 1016 to 1014 cm −3. For low boron concentration of 1.6×1014 cm−3, the leakage current level as low as 1.7×10−9 A/cm2 has been achieved by a 450 °C postimplantation annealing. © 1996 American Institute of Physics.

Notes: Using highly controlled ultraclean processing technology, marked improvements in n+p Si junction quality are achieved presenting a theoretical significance. Boron-doped substrates with various boron doping concentrations Ns were As+ implanted, forming the n+ junction sides. The diffusion (Id) and generation (Igen) currents, as well as the ideality and the generation factors, are significantly reduced, and bulk generation lifetimes are prolonged. Using Shockley–Read–Hall theory it is found that a deviation of the trapping centers energy (Et) from the midband-gap energy (Ei) is responsible for the improvements. The experimental results show that |Et−Ei| is a function of Ns, and that the Igen/Id ratio is significantly low. Accordingly, it is proposed that Igen/Id ratio should be regarded, under certain conditions, as a figure of merit for junction quality. It is concluded that the |Et−Ei| deviation is related to the ultraclean processing technology used, due to the formation of new energy levels far from Ei and the suppression of introduction of new energy levels near Ei. Surface generation currents were found experimentally to be significant, and thus not negligible. Surface effects in general demonstrated similar trends to the bulk generation effects. © 1997 American Institute of Physics.

Notes: The conduction mechanism and origin of the electrical stress-induced leakage current (SILC) in thin silicon dioxide (SiO2) films thermally grown on silicon substrate were clarified from various electrical properties. The properties examined consisted of the I-V characteristics, the oxide trap charge buildup, the generation of the Si/SiO2 interface states, and the generation of the neutral oxide traps. The electrical properties were obtained from films of different oxide thicknesses fabricated by different oxidation processes. The conduction mechanism of SILC was investigated from the viewpoint of oxide thickness dependence, using 92- and 56-A(ring)-thick oxide films. From the oxide-thickness-dependent studies it was found that the SILC phenomenon was not correlated with the oxide trap charge buildup and interface state generation, but rather closely correlated with neutral electron trap generation. The conduction mechanism for nonequilibrium SILC was theoretically deduced from one-dimensional ballistic triangular barrier tunneling that occurred only during the filling process. The tunneling was directed from a leakage spot at the electron-injecting cathode to neutral electron trap sites uniformly generated within the oxide at a trap level (≈1.17 eV from the cathode conduction band and ≈2.0 eV from the SiO2 conduction band) lower than the SiO2 barrier height during only the filling process. The origin of the SILC was also investigated from the viewpoint of oxidation process dependence, using both wet and dry oxides of 86 and 50 A(ring) thicknesses. The oxidation-process-dependent studies revealed that the SILC associated with a wet oxide after the stress application was less than that of a stressed dry oxide. The oxide trap charge buildup and the interface state generation associated with a wet oxide after the stress application was, however, greater than that of a stressed dry oxide. This result suggested that the SILC originated not from water-related chemical reactions, but from the distortion of the thermally grown SiO2 bond structure during electrical stressing. The SILC of both wet and dry oxides after the application of stress were well fitted by Fowler-Nordheim lines, confirming that the leakage conduction mechanism is independent of the oxidation process. © 1996 American Institute of Physics.

Notes: In low-temperature (300–350 °C) silicon epitaxy employing low-energy inert-gas ion bombardment on a growing film surface, the effects of ion bombardment energy and ion flux as well as that of ion species on the crystallinity of a grown silicon film have been experimentally investigated. It is shown that the energy dose determined by the product of ion energy and ion flux is a main factor for epitaxy that compensates for the reduction in the substrate temperature. Large-mass, large-radius ion bombardment using Xe has been demonstrated to be more effective in promoting epitaxy at low substrate temperatures than Ar ion bombardment. Thus, low-energy, high-flux, large-mass ion bombardment is the direction to pursue for further reducing the processing temperature while preserving high crystallinity of grown films. © 1996 American Institute of Physics.

Notes: Heavily phosphorus-doped polycrystalline silicon films (n+ poly-Si) were etched in a pure chlorine plasma using an ultraclean electron cyclotron resonance etcher. Compared against undoped polycrystalline etching, horizontal etch rates were too high to allow anisotropic etching of n+ poly-Si. With the addition of more than about 10% N2, highly anisotropic etches of n+ poly-Si can be obtained simultaneously with selectivities as high as 160 to SiO2 in a 4 mTorr plasma. These results are significant to lower submicron fabrication. X-ray photoelectron spectroscopy studies show that Si—N bonds are formed on the n+ poly-Si surface during etching and it is proposed that this layer protects the sidewall against Cl radicals in a N2/Cl2 plasma. The suppression of SiO2 etching by O2 addition to a N2/Cl2 plasma has also been demonstrated.

Notes: Using a newly developed ultraclean electron cyclotron resonance plasma etcher, Si wafers masked by SiO2 were etched with a chlorine plasma at pressures of 0.6–4.0 mTorr with a microwave power of 300–700 W. Ultraclean processing under a low ion energy condition at high pressures has revealed that there is an induction period during which time there is no SiO2 etching. This is not observed with Si. During the induction period, perfectly selective etching for Si to SiO2 has been achieved. Under this perfectly selective condition, anisotropic tenth micron patterns of polycrystalline silicon have been obtained with little undercut.

Notes: An ultraclean hot-wall low-pressure chemical vapor deposition (CVD) system was developed and Si films were deposited on single-crystal Si and SiO2 using ultraclean SiH4 and H2 gases in the temperature range 600–850 °C under an ultraclean environment. As a result of ultraclean processing, an incubation period of Si deposition only on SiO2 was found, and low-temperature Si selective deposition and epitaxy on Si were achieved without addition of HCl under deposition conditions where only nonselective polycrystalline Si growth could be obtained in conventional CVD systems.

Notes: Electrical properties of epitaxial silicon layers formed at very low temperatures of 320–350 °C by a low kinetic energy particle process are presented. Dopant impurities in the target material are substitutionally incorporated into the epitaxially grown layer, thus being electrically activated without any additional heat cycles. An epitaxial silicon layer having a resistivity as low as 0.0018 Ω cm has been obtained using a heavily arsenic-doped silicon target. A p-n junction diode formed by directly depositing an n-type epilayer on a p-type substrate exhibits a reverse current level as low as 1.88×10−9 A/cm2 at a reverse-bias voltage of 5 V. The electrical properties of the grown film have shown a good correlation to the crystallinity of the film, which changes depending upon the ion bombardment energy.

Notes: Ultralow contact resistance of metal silicide-n+-Si contact has been achieved by a novel contact metallization process employing Ta silicidation of a n+-Si contact surface by a Si-capping silicidation technique. The Si-capping silicidation has been employed to realize an ultraclean silicidation. The as-deposited Ta surface is in situ covered with a very thin Si protection layer in order to prevent the metal surface from being oxidized or contaminated. By combining the oxide-layer-free Si/metal on Si deposition process and an ultraclean ion implantation for mixing, metal silicide-n+Si structure has been formed by low temperature thermal annealing in an ultraclean Ar gas. As a result, an ultralow contact resistivity of 5.8×10−9 (Ω cm2) has been achieved.