ISSN:
1572-8102
Keywords:
The computer industry, standards, Futurebus+
;
multiple data stream architectures, interconnection architectures
;
network protocols, protocol verification
Source:
Springer Online Journal Archives 1860-2000
Topics:
Computer Science
Notes:
Abstract We used a hardware description language to construct a formal model of the cache coherence protocol described in the IEEE Futurebus+standard. By applying temporal logic model checking techniques, we found errors in the standard. The result of our project is a concise, comprehensible and unambiguous model of the protocol that should be useful both to the Futurebus+Working Group members, who are responsible for the protocol, and to actual designers of Futurebus+boards.
Type of Medium:
Electronic Resource
URL:
http://dx.doi.org/10.1007/BF01383968
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