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  • 1
    Electronic Resource
    Electronic Resource
    Springer
    Journal of electronic testing 8 (1996), S. 47-60 
    ISSN: 1573-0727
    Keywords: transition delay and path delay faults ; fault detectabilities ; fault coverage ; random patterns ; statistical delay fault analysis
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract In this paper we present a technique to statistically estimate transition delay and path delay fault coverage. The basic method is an extension of STAFAN to include delay faults. By partitioning a combinational circuit into non-overlapping fanout free logic cones, we accurately calculate the transition sensitization controllabilities of 0 ⇀ 1 and 1 ⇀ 0 transitions of the lines within a fanout free logic cone to the output of the fanout free logic cone for each fanout free logic cone. A strategy to calculate the transition observabilities of fanout stems is proposed. The detectability of a path delay fault is evaluated as the product of the observabilities of the input line to its head gate within each fanout free logic cone on the path multiplied by the transition controllability of the path. When compared with the fault simulations, the estimations of transition delay fault coverage are within 2.3%. Also, the technique gives reasonably good path delay fault coverage estimation for large fault set of the ISCAS85 benchmark circuits.
    Type of Medium: Electronic Resource
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  • 2
    Electronic Resource
    Electronic Resource
    Springer
    Journal of electronic testing 4 (1993), S. 225-235 
    ISSN: 1573-0727
    Keywords: Neural networks ; stuck-open and gate delay faults ; test pattern generation
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract In this article, an automatic test pattern generation technique using neural network models for stuck-open faults in CMOS combinational circuits is presented. For a gate level fault model of stuck-open faults in CMOS circuits, SR(slow-rise) and SF(slow-fall) gate transition faults we develop a neural network representation. A neural network computation technique for generating robust test patterns for stuck-open faults is given. The main result is extending previous efforts in stuck-at test pattern generation to stuck-open test pattern generation using neural network models. A second result is an extension of the technique to robust test pattern generation.
    Type of Medium: Electronic Resource
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  • 3
    Publication Date: 1989-09-01
    Print ISSN: 0021-9991
    Electronic ISSN: 1090-2716
    Topics: Computer Science , Physics
    Published by Elsevier
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