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    Electronic Resource
    Electronic Resource
    On partitioning and fault tolerance issues for neural array processors (1993)
    Springer
    The journal of VLSI signal processing systems for signal, image, and video technology 6 (1993), S. 85-94 
    Details
    ISSN: 1573-109X
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract In this article, we have studied time-efficient schedule and fault-tolerant design of partitioned array processors for neural networks. First, we have applied the locally-sequential-globally-parallel (LSGP) partitioning scheme to decompose large-size neural network algorithms so that they can be mapped into array processors of smaller size. Then we have derived an optimal latency schedule, i.e., for the same decomposition the schedule outperforms any other schedule, in terms of overall execution time. We have further proposed an algorithm-based fault tolerance (ABFT) method to guarantee higher reliability for the array processor implementation.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF01581962
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