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  • 1
    Electronic Resource
    Electronic Resource
    Springer
    Journal of electronic testing 5 (1994), S. 19-28 
    ISSN: 1573-0727
    Keywords: Input encoding ; output encoding ; self-checking ; unidirectional error
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract This article presents novel input and output encoding techniques such that the resulting circuit is bidirectional error-free. The circuit can be fully optimized and any types of gates can be used. These schemes are used to design the functional part of a self-checking circuit. The input encoding algorithm can be applied to any circuit without significantly increasing the input lines. The output encoding technique involves graph-embedding which is done with heuristic method of polynomial complexity. The heuristic technique produces nearly optimal output encoding. Previously published work restrict the types of gates used in the circuit to non-inversion gates (AND/OR), and use inverters only at the inputs. The proposed techniques have a clear advantage over the currently available techniques because they allow the use of any types of gates. These techniques do not necessarily increase the overhead when applied to different MCNC benchmark circuits as the experimental results indicate. The only restriction is that either the inputs or the outputs have to be symbolic, and the two-level description of a circuit has to be given.
    Type of Medium: Electronic Resource
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  • 2
    Publication Date: 1994-01-01
    Description: This paper presents a technique for designing interacting finite state machines which will be totally self-checking for any single stuck-at fault. In the proposed technique m-out-of-n codes are used for both primary output and state assignments. In addition, the next state logic (NSL) for each submachine and the output logic (OL) are realized such that any single stuck-at fault results in either single bit error or unidirectional multibit error at the output. The proposed technique does not have any restriction on the way the NSL and the OL are implemented.
    Print ISSN: 1065-514X
    Electronic ISSN: 1563-5171
    Topics: Electrical Engineering, Measurement and Control Technology
    Published by Hindawi
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  • 3
    Publication Date: 1994-01-01
    Description: This paper presents techniques for designing arbitrary combinational circuits so that any single stuck-at fault will result in either single bit error or unidirectional multibit error at the output. If the outputs are encoded using Berger code or m-out-of-n code, then the proposed technique will enable on-line detection of faults in the circuit. An algorithm for indicating whether a certain fault at an input will create bidirectional error at the output is presented. An input encoding algorithm and an output encoding algorithm that ensure that every fault will either produce single bit error or unidirectional multibit error at the output are proposed. If there are no input fault which produces bidirectional error, no internal stuck-at fault will result in such an error irrespective of the way the circuit is implemented. Thus, only single bit or unidirectional multibit error will result in the presence of a fault in the circuit. The proposed techniques have been applied to MCNC benchmark circuits and the overhead is estimated.
    Print ISSN: 1065-514X
    Electronic ISSN: 1563-5171
    Topics: Electrical Engineering, Measurement and Control Technology
    Published by Hindawi
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  • 4
    Publication Date: 1998-01-01
    Print ISSN: 1065-514X
    Electronic ISSN: 1563-5171
    Topics: Electrical Engineering, Measurement and Control Technology
    Published by Hindawi
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  • 5
    Publication Date: 2000-01-01
    Print ISSN: 1065-514X
    Electronic ISSN: 1563-5171
    Topics: Electrical Engineering, Measurement and Control Technology
    Published by Hindawi
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  • 6
    Publication Date: 1998-01-01
    Description: A technique for designing totally self-checking (TSC) FCMOS (Fully Complementary MOS) designs for multiple faults is presented in this paper. The existing techniques for self checking design consider only single faults, and suffer from high silicon area overhead. The multiple faults considered in this paper are multiple breaks, multiple transistors stuck-offs and multiple transistors stuck-ons. Starting from FCMOS design, small modifications (addition of two-weak transistors) make the original circuit totally self-checking. Experiemntal results show the overhead, delay and power consumption for the proposed technique. This paper also presents a technique for designing multistage TSC FCMOS circuits.
    Print ISSN: 1065-514X
    Electronic ISSN: 1563-5171
    Topics: Electrical Engineering, Measurement and Control Technology
    Published by Hindawi
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  • 7
    Publication Date: 2019-07-10
    Description: In this letter we present a timing and control strategy that can be used to realize synchronous systems with a level of performance that approaches that of asynchronous circuits or systems. This approach is based upon a single-phase synchronous circuit/system architecture with a variable period clock. The handshaking signals required for asynchronous self-timed circuits are not needed. Dynamic power supply current monitoring is used to generate the timing information, that is comparable to the completion signal found in self-timed circuits; this timing information is used to modi@ the circuit clock period. This letter is concluded with an example of the proposed approach applied to a static CMOS ripple-carry adder.
    Keywords: Computer Operations and Hardware
    Format: application/pdf
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