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  • 1
    Electronic Resource
    Electronic Resource
    Introduction (1989)
    Springer
    The journal of VLSI signal processing systems for signal, image, and video technology 1 (1989), S. 93-94 
    Details
    ISSN: 1573-109X
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF02477175
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    Paper (German National Licenses)
    Fulltext
  • 2
    Electronic Resource
    Electronic Resource
    Parallel and pipelined VLSI implementation of a staged decoder for BCM signals (1995)
    Springer
    The journal of VLSI signal processing systems for signal, image, and video technology 11 (1995), S. 195-211 
    Details
    ISSN: 1573-109X
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract This paper is devoted to VLSI implementation of a staged decoder for Block-Coded Modulation (BCM). We first review a general parallel and pipelined implementation of the decoder and we identify the parameters to be considered for optimization. A particular BCM scheme, based on the 8-PSK signal set, is chosen for a case study. Several ideas are described leading to a code-optimized design, and hardware implementation is shown. Next, we evaluate the performance of our design. In particular it is shown that, by exploiting regularity, a simple structure which achieves a throughput rate of 10 Mbps can be implemented by using 23 K transistors and 2Μ standard cells CMOS technology. Further optimization and simple stacking of ten processors on a single chip in a block-processing structure allows us to achieve a throughput rate of 100 Mbps with about 150 K transistors (38 K gates).
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF02107053
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    Paper (German National Licenses)
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  • 3
    Electronic Resource
    Electronic Resource
    Dynamic programming implementation on array processor architectures (1996)
    Springer
    The journal of VLSI signal processing systems for signal, image, and video technology 13 (1996), S. 27-35 
    Details
    ISSN: 1573-109X
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Dynamic Programming (DP) applies to many signal and image processing applications including boundary following, the Viterbi algorithm, dynamic time warping, etc. This paper presents an array processor implementation of generic dynamic programming. Our architecture is a SIMD array attached to a host computer. The processing element of the architecture is based on an ASIC design opting for maximum speed-up. By adopting a torus interconnection network, a dual buffer structure, and a multilevel pipeline, the performance of the DP chip is expected to reach the order of several GOPS. The paper discusses both the dedicated hardware design and the data flow control of the DP chip and the total array.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00930665
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    Paper (German National Licenses)
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  • 4
    Electronic Resource
    Electronic Resource
    Gradient Adaptive Algorithms for Contrast-Based Blind Deconvolution (2000)
    Springer
    The journal of VLSI signal processing systems for signal, image, and video technology 26 (2000), S. 47-60 
    Details
    ISSN: 1573-109X
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract This paper presents extensions of stochastic gradient independent component analysis (ICA) methods to the blind deconvolution task. Of particular importance in these extensions are the constraints placed on the deconvolution system transfer function. While unit-norm constrained ICA approaches can be directly applied to the prewhitened blind deconvolution task, an allpass filter constraint within the optimization procedure is more appropriate. We show how such constraints can be approximately imposed within gradient adaptive finite-impulse-response (FIR) filter implementations by proper extensions of gradient techniques within the Stiefel manifold of orthonormal matrices. Both on-line time-domain and block-based frequency-domain algorithms are described. Simulations verify the superior performance behaviors provided by our allpass-constrained algorithms over standard unit-norm-constrained ICA algorithms in blind deconvolution tasks.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1008191316248
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    Paper (German National Licenses)
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  • 5
    Electronic Resource
    Electronic Resource
    Editorial (1991)
    Springer
    The journal of VLSI signal processing systems for signal, image, and video technology 3 (1991), S. 147-147 
    Details
    ISSN: 1573-109X
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00925824
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    Paper (German National Licenses)
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  • 6
    Electronic Resource
    Electronic Resource
    Parallel algorithms/architectures for neural networks (1989)
    Springer
    The journal of VLSI signal processing systems for signal, image, and video technology 1 (1989), S. 221-251 
    Details
    ISSN: 1573-109X
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract This paper advocates digital VLSI architectures for implementing a wide variety of artificial neural networks (ANNs). A programmable systolic array is proposed, which maximizes the strength of VLSI in terms of intensive and pipelined computing and yet circumvents the limitation on communication. The array is meant to be more general purpose than most other ANN architectures proposed. It may be used for a variety of algorithms in both the retrieving and learning phases of ANNs: e.g., single layer feedback networks, competitive learning networks, and multilayer feed-forward networks. A unified approach to modeling of existing neural networks is proposed. This unified formulation leads to a basic structure for a universal simulation tool and neurocomputer architecture. Fault-tolerance approach and partitioning scheme for large or non-homogeneous networks are also proposed. Finally, the implementations based on commercially available VLSI chips (e.g., Inmos T800) and custom VLSI technology are discussed in great detail.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF02427796
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    Paper (German National Licenses)
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  • 7
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    Accurate detection of aneuploidies in array CGH and gene expression microarray data (2004)
    Oxford University Press
    Details
    Publication Date: 2004-07-29
    Print ISSN: 1367-4803
    Electronic ISSN: 1460-2059
    Topics: Biology , Computer Science , Medicine
    Published by Oxford University Press
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    PAPER CURRENT
  • 8
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    Real-time optical associative retrieval technique (1986)
    In:  Other Sources
    Details
    Publication Date: 2011-08-19
    Description: A real-time optical associative retrieval technique is presented. The associative retrieval model enables a large amount of data to be stored and recalled by partial information optically in real time. The real-time capability is achieved by using an electronically addressed spatial light modulator based on the pocket-size liquid crystal display television. The potential application of the technique to the perceptive vision requirements in telerobotics for achieving NASA's goals of automation in space is described.
    Keywords: COMPUTER OPERATIONS AND HARDWARE
    Type: Optical Engineering (ISSN 0091-3286); 25; 853-856
    Format: text
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    NASA TECHNICAL REPORTS
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