Publication Date:
1994-01-01
Description:
Test generation for sequential VLSI circuits has remained a difficult problem to solve. The difficulty arises because of reasoning about temporal behavior of sequential circuits. We use temporal logic to model digital circuits. Temporal Logic can model circuits hierarchically. A set of heuristics is given to aid during test generation. A hierarchical test generation algorithm is proposed.
Print ISSN:
1065-514X
Electronic ISSN:
1563-5171
Topics:
Electrical Engineering, Measurement and Control Technology
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