Publication Date:
2019-06-27
Description:
After amplification and normalization, incoming data bits are fed, alternately, to pair of integrators. While one integrator is operating, content of other is on hold, sample, and dump. Clock derived in bit-timing extractor times and controls integrators. Frequency of clock is one-half data rate.
Keywords:
ELECTRONIC SYSTEMS
Type:
MSC-14264
Format:
application/pdf
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