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  • 1
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    Instruction manual for epitaxial apparatus (1965)
    In:  CASI
    Details
    Publication Date: 2019-05-29
    Description: Instruction manual for apparatus using programmer operation of electronic valves for etching and growth of single crystal silicon, deposition of silicon dioxide, and nucleation site treatment
    Keywords: MACHINE ELEMENTS AND PROCESSES
    Type: NASA-CR-74954
    Format: application/pdf
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  • 2
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    A method for polycrystalline silicon delineation applicable to a double-diffused MOS transistor (1974)
    In:  CASI
    Details
    Publication Date: 2019-06-27
    Description: Method is simple and eliminates requirement for unreliable special etchants. Structure is graded in resistivity to prevent punch-through and has very narrow channel length to increase frequency response. Contacts are on top to permit planar integrated circuit structure. Polycrystalline shield will prevent creation of inversion layer in isolated region.
    Keywords: ELECTRONIC COMPONENTS AND CIRCUITS
    Type: LAR-11536 , LAR-11598
    Format: application/pdf
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  • 3
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    Shielded silicon gate complementary MOS integrated circuit. (1972)
    In:  Other Sources
    Details
    Publication Date: 2019-06-27
    Description: An electrostatic shield for complementary MOS integrated circuits was developed to minimize the adverse effects of stray electric fields created by the potentials in the metal interconnections. The process is compatible with silicon gate technology. N-doped polycrystalline silicon was used for all the gates and the shield. The effectiveness of the shield was demonstrated by constructing a special field plate over certain transistors. The threshold voltages obtained on an oriented silicon substrate ranged from 1.5 to 3 V for either channel. Integrated inverters performed satisfactorily from 3 to 15 V, limited at the low end by the threshold voltages and at the high end by the drain breakdown voltage of the n-channel transistors. The stability of the new structure with an n-doped silicon gate as measured by the shift in C-V curve under 200 C plus or minus 20 V temperature-bias conditions was better than conventional aluminum gate or p-doped silicon gate devices, presumably due to the doping of gate oxide with phosphorous.
    Keywords: ELECTRONIC EQUIPMENT
    Format: text
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  • 4
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    Experimental investigation of a double-diffused MOS structure (1976)
    In:  CASI
    Details
    Publication Date: 2019-06-27
    Description: Self-aligned polysilicon gate technology was applied to double-diffused MOS (DMOS) construction in a manner that retains processing simplicity and effectively eliminates parasitic overlap capacitance because of the self-aligning feature. Depletion mode load devices with the same dimensions as the DMOS transistors were integrated. The ratioless feature results in smaller dimension load devices, allowing for higher density integration with no increase in the processing complexity of standard MOS technology. A number of inverters connected as ring oscillators were used as a vehicle to test the performance and to verify the anticipated benefits. The propagation time-power dissipation product and process related parameters were measured and evaluated. This report includes (1) details of the process; (2) test data and design details for the DMOS transistor, the load device, the inverter, the ring oscillator, and a shift register with a novel tapered geometry for the output stages; and (3) an analytical treatment of the effect of the distributed silicon gate resistance and capacitance on the speed of DMOS transistors.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: NASA-CR-2620
    Format: application/pdf
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  • 5
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    Effect of silicon-gate resistance on the frequency response of MOS transistors (1975)
    In:  Other Sources
    Details
    Publication Date: 2019-06-27
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: IEEE Transactions on Electron Devices; ED-22; May 1975
    Format: text
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  • 6
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    Optimum load device for DMOS integrated circuits (1976)
    In:  Other Sources
    Details
    Publication Date: 2019-06-27
    Description: Depletion-mode load devices can be integrated with DMOS transistors without any extra diffusions or ion implantation processing steps by judicious choice of the substrate crystal orientation and resistivity. For low voltage operation line-type 1, 1, 1 crystal orientation should be used. The line-type 1, 1, 1 crystal orientation also yields a higher transconductance for the DMOS transistor than the line-type 1, 0, 0 orientation. The geometry of the load device and the DMOS transistor can be made ratioless to conserve area. Self-aligned gates, hitherto considered incompatible with DMOS transistors, have been incorporated in the structure. The experimental DMOS inverters, using a conservative design, have achieved 4-ns propagation delay, 1.3-V operation, and 2-pJ propagation delay-power dissipation product.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: IEEE Journal of Solid-State Circuits; SC-11; Aug. 197
    Format: text
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  • 7
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    Improved process for epitaxial deposition of silicon on prediffused substrates (1968)
    In:  CASI
    Details
    Publication Date: 2019-06-27
    Description: Process for fabricating integrated circuits uniformly deposits silicon epitaxially on prediffused substrates without affecting the sublayer diffusion pattern. Two silicon deposits from different sources, and deposited at different temperatures, protect the sublayer pattern from the silicon tetrachloride reaction.
    Keywords: MATERIALS
    Type: MFS-14910
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  • 8
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    Experimental investigation of a shielded complementary Metal-Oxide Semiconductor (MOS) structure (1974)
    In:  CASI
    Details
    Publication Date: 2019-07-13
    Description: A shielded integrated complimentary MOS transistor structure is described which is used to prevent field inversion in the region not occupied by the gates and which permits the use of a thinner field oxide, reduces the chip area, and has provision for simplified multilayer connections. The structure is used in the design of a static shift register and results in a 20% reduction in area.
    Keywords: PHYSICS, SOLID-STATE
    Type: NASA-CR-132456
    Format: application/pdf
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