Publication Date:
2019-08-28
Description:
An iterative, simulation-based design procedure for a neural network chip is introduced. For this design procedure, the goal is to produce a chip layout for a neural network in which the weights are determined by transistor gate width-to-length ratios. In a given iteration, the current layout is simulated using the circuit simulator SPICE, and layout adjustments are made based on conventional gradient-decent methods. After the iteration converges, the chip is fabricated. Monte Carlo analysis is used to predict the effect of statistical fabrication process variations on the overall performance of the neural network chip.
Keywords:
ELECTRONICS AND ELECTRICAL ENGINEERING
Type:
In: WNN 92; Proceedings of the 3rd Workshop on Neural Networks: Academic(Industrial)NASA/Defense, Auburn Univ., AL, Feb. 10-12, 1992 and South Shore Harbour, TX, Nov. 4-6, 1992 (A93-50726 21-63); p. 401-408.
Format:
text
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