ALBERT

Notes: Electron, ion, and x-ray lithography are all being advocated as replacements for optical lithography at some time in the future for high-volume production of integrated circuits. Of some concern is the potential for radiation damage to underlying circuit layers caused by these lithographies. In this paper we report results of an experiment designed specifically to compare damage to radiation-hardened circuits arising from the three nonoptical lithographic technologies. We employ flood exposures of metal-oxide-semiconductor (MOS) capacitors by electrons, ions, and x rays to simulate lithographic exposures. We report results of characterizations by capacitance-voltage analysis, radiation-hardness testing, and bias-stress testing. Degradation in radiation hardness is used as measure of residual damage caused by the simulated lithographic irradiations that is not annealed out at low temperatures. We find minimal damage to the oxide resulting from lithographic doses of ions. We measure voltage shifts due to oxide- and interface-trap charge introduced by x rays and electrons and find that they can be removed by standard post-metallization anneals. We find that the radiation tolerance of MOS capacitors so irradiated and annealed is nearly identical to that of devices that did not see irradiation and annealing. Moreover, in all cases, no bias-temperature instabilities resulted from the exposure-anneal sequences. We find that all three types of lithographic techniques are promising candidates for use in advanced, radiation-hardened integrated circuit technologies.

Notes: We have identified several features of the 1/f noise and radiation response of metal-oxide-semiconductor (MOS) devices that are difficult to explain with standard defect models. To address this issue, and in response to ambiguities in the literature, we have developed a revised nomenclature for defects in MOS devices that clearly distinguishes the language used to describe the physical location of defects from that used to describe their electrical response. In this nomenclature, "oxide traps'' are simply defects in the SiO2 layer of the MOS structure, and "interface traps'' are defects at the Si/SiO2 interface. Nothing is presumed about how either type of defect communicates with the underlying Si. Electrically, "fixed states'' are defined as trap levels that do not communicate with the Si on the time scale of the measurements, but "switching states'' can exchange charge with the Si. Fixed states presumably are oxide traps in most types of measurements, but switching states can either be interface traps or near-interfacial oxide traps that can communicate with the Si, i.e., "border traps'' [D. M. Fleetwood, IEEE Trans. Nucl. Sci. NS-39, 269 (1992)]. The effective density of border traps depends on the time scale and bias conditions of the measurements. We show the revised nomenclature can provide focus to discussions of the buildup and annealing of radiation-induced charge in non-radiation-hardened MOS transistors, and to changes in the 1/f noise of MOS devices through irradiation and elevated-temperature annealing.Border-trap densities of ∼1010–1011 cm−2 are inferred from changes in switching-state density during postirradiation annealing, and from a simple trapping model of the 1/f noise in MOS devices. We also present a detailed study of charge buildup and annealing in MOS capacitors with radiation-hardened oxides through steady-state and switched-bias postirradiation annealing. Trapped-hole, trapped-electron, and switching-state densities are inferred via thermally stimulated current and capacitance-voltage measurements. A lower bound of ∼3×1011 cm−2 is estimated for the effective density of border traps that contribute to the electrical response of the irradiated devices. This is roughly 20% of the observed switching-state density for these devices and irradiation conditions. To our knowledge, this represents the first quantitative separation of measured switching-state densities into border-trap and interface-trap components. Possible physical models of border traps are discussed. E' centers in SiO2 (trivalent Si centers associated with oxygen vacancies) may serve as border traps in many irradiated MOS devices.

Notes: We have combined thermally stimulated-current (TSC) and capacitance–voltage (C–V) measurements to estimate oxide, interface, and effective border trap densities in 6–23 nm thermal, N2O, and N2O-nitrided oxides exposed to ionizing radiation or high-field electron injection. Defect densities depend strongly on oxide processing, but radiation exposure and moderate high-field stress lead to similar trapped hole peak thermal energy distributions (between ∼1.7 and ∼2.0 eV) for all processes. This suggests that similar defects dominate the oxide charge trapping properties in these devices. Radiation-induced hole and interface trap generation efficiencies (0.1%–1%) in the best N2O and N2O-nitrided oxides are comparable to the best radiation hardened oxides in the literature. After ∼10 Mrad(SiO2) x-ray irradiation or ∼10 mC/cm2 constant current Fowler–Nordheim injection, effective border trap densities as high as ∼5×1011 cm−2 are inferred from C–V hysteresis. These measurements suggest irradiation and high-field stress cause similar border trap energy distributions. In each case, even higher densities of compensating trapped electrons in the oxides (up to 2×1012 cm−2) are inferred from combined TSC and C–V measurements. These trapped electrons prevent conventional C–V methods from providing accurate estimates of the total oxide trap charge density in many irradiation or high-field stress studies. Fewer compensating electrons per trapped hole (∼26%±5%) are found for irradiation of N2O and N2O-nitrided oxides than for thermal oxides (∼46%±7%). More compensating electrons are also found for high-field electron injection than radiation exposure, emphasizing the significance of border traps to metal-oxide-semiconductor long term reliability. The primary effect of nitrogen on charge trapping in these oxides appears to be improvement of the near interfacial oxide in which border traps are found.

Notes: We find a strong correlation between preirradiation channel resistance and radiation-induced interface-trap charge in n-channel metal-oxide-semiconductor (MOS) transistors. While it has long been known that the postirradiation mobility of MOS transistors degrades with exposure to ionizing radiation, we believe this is the first time that differences in the postirradiation interface-trap charge have been linked to differences in preirradiation device parameters. A simple model is presented that relates the observed variations in preirradiation channel resistance to scattering from defects at the Si/SiO2 interface which may be precursors to the radiation-induced interface-trap charge.

Notes: Trivalent silicon Pb0 and Pb1 defects were identified at both the top Si(100)/buried-SiO2 and buried-SiO2/bottom-Si(100) interfaces in high-temperature (1320 °C) annealed Si/SiO2/Si struc- tures. The paramagnetic defects are generated by annealing in a flow of pure nitrogen (N2) or forming gas [N2H2; 95:5 (by volume)] at 550 °C. In addition, the forming-gas anneal also generated positive charge in the buried oxides; significant lateral nonuniformities in the buried oxide charge density were observed following this anneal. These macroscopic inhomogeneities may be linked to previous reports of homogeneity related problems involving the SIMOX buried oxide, such as early breakdown and etch pits, suggesting that these types of measurements may be useful as nondestructive screens of SIMOX wafer quality. © 1996 American Institute of Physics.

Notes: A new technique is proposed to evaluate the radiation response of metal-oxide-semiconductor (MOS) transistors. The method requires that otherwise identical n- and p-channel transistors be irradiated under the same conditions. Using assumptions similar to those of widely accepted "single-transistor'' methods, standard threshold-voltage and mobility measurements are combined to accurately estimate threshold-voltage shifts due to oxide-trapped charge and interface traps. This approach is verified for several MOS processes. The dual-transistor method can be applied to devices with much larger parasitic leakage, and at shorter times following a radiation pulse, than subthreshold current or charge-pumping techniques.

Notes: The response of metal-oxide-semiconductor (MOS) transistors and capacitors to high-energy Co-60 gamma and low-energy x-ray irradiation is evaluated as a function of gate bias during exposure. It is demonstrated that, in contrast to previous expectations, the relative response of MOS devices to Co-60 gamma and 10 keV x-ray irradiation cannot be explained simply in terms of electron-hole recombination and dose enhancement effects.

Notes: Thermally stimulated current (TSC) and capacitance–voltage measurements are combined via a newly developed analysis technique to estimate positive and negative oxide-trap charge densities for metal–oxide–semiconductor (MOS) capacitors exposed to ionizing radiation or subjected to high-field stress. Significantly greater hole trapping than electron trapping is observed in 3% borosilicate glass (BSG) insulators. Two prominent TSC peaks are observed in these BSG films. A high-temperature peak near 250 °C is attributed to the Eγ′ defect, which is a trivalent Si center in SiO2 associated with an O vacancy. A lower temperature positive charge center near 100 °C in these films is likely to be impurity related. The higher temperature Eγ′ peak is also observed in 10, 17, and 98 nm thermal oxides. A much weaker secondary peak is observed near ∼60 °C in some devices, which likely is due to metastably trapped holes in the bulk of the SiO2. Negative charge densities in these thermal oxides are primarily associated with electrons in border traps, which do not contribute to TSC, as opposed to bulk electron traps, which can contribute to TSC. Ratios of electron to hole trap densities in the thermal oxides range from ∼30% for radiation exposure to greater than 80% for high-field stress. It is suggested that the large densities of border traps associated with trapped holes in these devices may be due to high space-charge induced electric fields near the Si/SiO2 interface. In some instances, border traps can reduce near-interfacial electric fields by local compensation of trapped positive charge. This may provide a natural explanation for the large densities of border traps often observed in irradiated or electrically stressed MOS capacitors. © 1998 American Institute of Physics.

Notes: Total dose radiation hardness measurements were performed on silicon-on-insulator (SOI) test structures where the insulator is chemical vapor deposited (CVD) diamond. These measurements represent a first look at the fundamental radiation response of low-pressure CVD synthetic diamond materials for SOI applications. Silicon/diamond metal-insulator-semiconductor (MIS) capacitors were subjected to both cobalt-60 and 10 keV x-ray irradiation up to doses of 1×107 rad (SiO2) while under positive, negative, and zero bias conditions. The diamond insulators used in these devices were found to be free from extensive hole or electron trapping. This behavior is consistent with the high electron and hole mobility of the polycrystalline diamond insulator.