ISSN:
1573-0727
Keywords:
FPGA
;
test
;
ATPG
;
iterative testing
Source:
Springer Online Journal Archives 1860-2000
Topics:
Electrical Engineering, Measurement and Control Technology
Notes:
Abstract This paper describes an approach to minimize the number of test configurations for testing the logic cells of a RAM-based FPGA taking into account the configurability of such flexible device. The proposed approach concerns the XILINX 4000 family. On this example of FPGA, a bottom-up test technique is first used to generate test configurations for the elementary modules, then test configurations for a single logic cell, and finally test configurations for the m × m array of logic cells. In this bottom-up technique, it is shown that the key point is the minimization of the number of test configurations for a logic cell. An approach for the logic cell of the XILINX4000 family is then described to define a minimum number of test configurations knowing the test configurations of its logic modules. This approach gives only 5 test configurations for the XILINX4000 family while the previous published works concerning Boolean testing of this FPGA family gives 8 or 21 test configurations.
Type of Medium:
Electronic Resource
URL:
http://dx.doi.org/10.1023/A:1008355701933
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