ISSN:
1573-0727
Keywords:
VLSI
;
FPGA
;
test
;
ATPG
Source:
Springer Online Journal Archives 1860-2000
Topics:
Electrical Engineering, Measurement and Control Technology
Notes:
Abstract This paper addresses the problem of testing the configurable modules used in the local interconnect of SRAM-based FPGAs. First, it is demonstrated that a n address bit Configurable Interface Multiplexer requires N = 2 n test configurations considering a stuck-at as well as a functional fault model. Second, a logic cell with a set of k input Configurable Interface Modules with n address bits is analyzed and it is proven that the set of CIMs can be tested in parallel making the number of required test configurations equal to N = 2 n . Third, it is shown that the complete circuit i.e. a m × m array of sets of k Configurable Interface Multiplexers with n address bits can be tested with only N = 2 n test configurations using the XOR tree and shift register structures.
Type of Medium:
Electronic Resource
URL:
http://dx.doi.org/10.1023/A:1008376917755
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