ISSN:
1433-299X
Keywords:
Formal specification
;
VLSI design
;
Complexity
;
Performance estimation
Source:
Springer Online Journal Archives 1860-2000
Topics:
Computer Science
Notes:
Abstract Conditions necessary to produce correct asymptotic complexity results and realistic performance estimates for VLSI devices, using discrete high-level VLSI complexity models, are examined. A set of design constraints is formulated, based on results from two experiments involving suitably designed and fabricated VLSI devices. The basis of the complexity model is modified so that it satisfies the constraints. A case-study for an integer multiplier design shows that the modified model produces asymptotic results in agreement with empirical measurements. Low-level performance estimates are then obtained using the RC network delay model in conjunction with the VLSI complexity model.
Type of Medium:
Electronic Resource
URL:
http://dx.doi.org/10.1007/BF01211303
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