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  • 1
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    Digital GPS-Signal Processor With P-Code/No-P-Code Option (1994)
    In:  Other Sources
    Details
    Publication Date: 2019-07-13
    Description: Size, power, and cost reduced by exploiting commonality. Digital signal processor for Global Positioning System (GPS) receiver set to operate in "code" mode when P code known, or in "codeless" mode when P code not known. In codeless mode, processor performs full-quadrature processing, resulting in signal-to-noise ratio (SNR) 6 dB greater than SNR's of processors not performing at full quadrature.
    Keywords: ELECTRONIC SYSTEMS
    Type: NPO-18831 , NASA Tech Briefs (ISSN 0145-319X); 18; 5; P. 85
    Format: text
    Location Call Number Expected Availability
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    NASA TECHNICAL REPORTS
  • 2
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    Unknown
    Chip Advancer For GPS Receiver (1989)
    In:  Other Sources
    Details
    Publication Date: 2019-07-12
    Description: Instrument errors made negligible. For each integration interval, both delay and rate of change of delay initialized to small fraction of chip - for example, to order of 10 to the negative 7th power - thereby making feedback control and extraction of delay highly accurate and flexible. With appropriate selection of sampling rate relative to chip rate, commensurability errors reduced to extremely small levels. In Global Positioning System (GPS) receiver, pseudorandom code sequence generated by simple digital logic incorporating effects of time, delay, and rate of change of delay. Flexibility in starting time and sum interval very useful in aligning correlation interval with beginnings and endings of data bits.
    Keywords: ELECTRONIC SYSTEMS
    Type: NPO-16996 , NASA Tech Briefs (ISSN 0145-319X); 13; 6; P. 40
    Format: text
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
    NASA TECHNICAL REPORTS
  • 3
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    Unknown
    Counterrotator And Correlator For GPS Receivers (1989)
    In:  Other Sources
    Details
    Publication Date: 2019-07-12
    Description: Accurate, all-digital, high-speed processor comprising correlator and down-converter developed for receivers in Global Positioning System (GPS). Processor reduces roundoff and commensurability errors to extremely small values. Use of digital chip and phase advancers provides outstanding control and accuracy in phase and feedback. Great flexibility imparted by provision for arbitrary starting time and integration length. Minimum-bit design requires minimum number of logical elements, thereby reducing size, power, and cost.
    Keywords: ELECTRONIC SYSTEMS
    Type: NPO-16998 , NASA Tech Briefs (ISSN 0145-319X); 13; 6; P. 34
    Format: text
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
    NASA TECHNICAL REPORTS
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