ISSN:
1573-0727
Keywords:
totally self-checking checkers
;
CMOS technology
;
conventional Berger code
;
Berger code
;
partitioning
;
1's counters
;
fully-testable circuits
Source:
Springer Online Journal Archives 1860-2000
Topics:
Electrical Engineering, Measurement and Control Technology
Notes:
Abstract A technique for designing efficient checkers for conventional Berger code is proposed in this paper. The check bits are derived by partitioning the information bits into two blocks, and then using an addition array to sum the number of 1's in each block. The check bit generator circuit uses a specially designed 4-input 1's counter. Two other types of 1's counters having 2 and 3 inputs are also used to realize checkers for variable length information bits. Several variations of 2-bit adder circuits are used to add the number of 1's. The check bit generator circuit uses gates with fan-in of less than or equal to 4 to simplify implementation in CMOS. The technique achieves significant improvement in gate count as well as speed over existing approaches.
Type of Medium:
Electronic Resource
URL:
http://dx.doi.org/10.1007/BF00134692
Permalink
