Electronic Resource
Woodbury, NY
:
American Institute of Physics (AIP)
Applied Physics Letters
79 (2001), S. 3812-3814
ISSN:
1077-3118
Source:
AIP Digital Archive
Topics:
Physics
Notes:
We propose and implement a promising fabrication technology for geometrically well-defined single-electron transistors based on a silicon-on-insulator quantum wire and side-wall depletion gates. The 30-nm-wide silicon quantum wire is defined by a combination of conventional photolithography and process technology, called a side-wall patterning method, and depletion gates for two tunnel junctions are formed by the doped polycrystalline silicon sidewall. The good uniformity of the wire suppresses unexpected potential barriers. The fabricated device shows clear single-electron tunneling phenomena by an electrostatically defined single island at liquid nitrogen temperature and insensitivity of the Coulomb oscillation period to gate bias conditions. © 2001 American Institute of Physics.
Type of Medium:
Electronic Resource
URL:
http://dx.doi.org/10.1063/1.1421081
Permalink
|
Location |
Call Number |
Expected |
Availability |
