ISSN:
1573-0727
Keywords:
MCM testing
;
boundary-scan
;
self-timed CMOS design
;
testing interconnections
Source:
Springer Online Journal Archives 1860-2000
Topics:
Electrical Engineering, Measurement and Control Technology
Notes:
Abstract This paper presents a self-timed scan-path architecture, to be used in a conventional synchronous environment, and with basic application in digital testing and interconnections checking in a Smart-Substrate MCM (T.A. García, A.J. Acosta, J.M. Mora, J. Ramos, and J.L. Huertas, “Self-Timed Boundary-Scan Cells for Multi-Chip Module Test,” Proceedings of IEEE VLSI Test Symposium, April 1998, pp. 92–97). With this approach, the potential advantages of self-timed asynchronous systems are explored for their practical use in a classical MCM testing application. Three different self-timed asynchronous boundary scan cells are proposed (Sense, Drive and Drive & Sense cells) that can be connected to form a self-timed scan-path. The main advantage is that no global test clock is needed, avoiding clock skew and synchronization faults in test mode, and hence, a more reliable test process is achieved. These cells have been designed and integrated in active substrates, building several boundary-scan configurations and being fully compatible with the ANSI/IEEE 1149.1 Standard. The experimental results, as well as their comparison with their synchronous counterparts, show the feasibility of the proposed self-timed approach for testing interconnections in a MCM.
Type of Medium:
Electronic Resource
URL:
http://dx.doi.org/10.1023/A:1008388318835
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