Publication Date:
2015-09-03
Description:
In this paper, three electrical techniques (frequency dependent conductance analysis, AC transconductance (AC-g m ), and positive gate bias stress) were used to evaluate three different gate dielectrics (Plasma-Enhanced Atomic Layer Deposition Si 3 N 4 , Rapid Thermal Chemical Vapor Deposition Si 3 N 4 , and Atomic Layer Deposition (ALD) Al 2 O 3 ) for AlGaN/GaN Metal-Insulator-Semiconductor High-Electron-Mobility Transistors. From these measurements, the interface state density (D it ), the amount of border traps, and the threshold voltage (V TH ) shift during a positive gate bias stress can be obtained. The results show that the V TH shift during a positive gate bias stress is highly correlated to not only interface states but also border traps in the dielectric. A physical model is proposed describing that electrons can be trapped by both interface states and border traps. Therefore, in order to minimize the V TH shift during a positive gate bias stress, the gate dielectric needs to have a lower interface state density and less border traps. However, the results also show that the commonly used frequency dependent conductance analysis technique to extract D it needs to be cautiously used since the resulting value might be influenced by the border traps and, vice versa, i.e., the g m dispersion commonly attributed to border traps might be influenced by interface states.
Print ISSN:
0003-6951
Electronic ISSN:
1077-3118
Topics:
Physics
Permalink