Publication Date:
2019-07-12
Description:
A new successive-approximation A/D converter is described. It combines a string of equal-valued polysilicon resistors and a set of ratioed capacitors in a unique circuit configuration so that a high sampling rate is achieved. The comparator is realized by a chopper-stabilized amplifier to reduce the effect of the offset voltages of MOS amplifiers. The converter performs an 8-b monotonic conversion with a differential nonlinearity less than 1 LSB in 770 nsec. The die area is 3750 sq mil. This new conversion technique can also be utilized in a pipelined A/D converter (Temes, 1985) and enables it to achieve high speed.
Keywords:
ELECTRONICS AND ELECTRICAL ENGINEERING
Type:
IEEE Journal of Solid-State Circuits (ISSN 0018-9200); 25; 880-885
Format:
text
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