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  • Articles  (4)
  • Articles: DFG German National Licenses  (4)
  • 1
    Electronic Resource
    Electronic Resource
    Woodbury, NY : American Institute of Physics (AIP)
    Applied Physics Letters 61 (1992), S. 2036-2038 
    ISSN: 1077-3118
    Source: AIP Digital Archive
    Topics: Physics
    Notes: Optoelectronic modulators and couplers frequently require high-aspect ratio feature definition in thick (≥10 μm) gold. The common process used involves up plating with a photoresist guide. Theory argues that feature boundaries would be degraded due to both diffractive spreading and scattering of the incident light in the resist. This is not observed and near-90° sidewalls appear obtainable. This letter demonstrates this effect and proposes an explanation for it.
    Type of Medium: Electronic Resource
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  • 2
    ISSN: 1572-8102
    Keywords: I/O systems ; formal design ; theorem-proving ; model checking
    Source: Springer Online Journal Archives 1860-2000
    Topics: Computer Science
    Notes: Abstract The transaction ordering problem of the original PCI 2.1 standard bus specification violates the desired correctness property of maintaining the so called ‘Producer/Consumer’ relationship between writers and readers of data. This violation stems mainly from the so called completion stealing problem, first identified and solved by Corella et al. [4], and supported by a formal paper and pencil argument. In this paper, we develop a flexible graph theory library in PVS for modeling computer bus structures, formalize the PCI 2.1 protocol containing the solution of [4] in it, and mechanically prove the absence of completion stealing. Next, we define the Producer/Consumer property in PVS and sketch its mechanical proof. Noting the complexity of this proof effort (unfinished as yet), we explore a combination of theorem proving and model-checking in which the model used for model-checking is made tractable by exploiting the formal theorems established during theorem-proving as well as several intuitively justified assumptions. The theorem-proving infrastructure we have built for modeling CPU interconnect structures is highly reusable. Our work is one example of a natural division of labor between theorem-proving and model-checking in tackling system-level verification problems under realistic time budgets.
    Type of Medium: Electronic Resource
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  • 3
    Electronic Resource
    Electronic Resource
    Springer
    Formal methods in system design 16 (2000), S. 5-6 
    ISSN: 1572-8102
    Source: Springer Online Journal Archives 1860-2000
    Topics: Computer Science
    Type of Medium: Electronic Resource
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  • 4
    Electronic Resource
    Electronic Resource
    Springer
    The journal of VLSI signal processing systems for signal, image, and video technology 7 (1994), S. 33-45 
    ISSN: 1573-109X
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Asynchronous/Self-Timed designs are beginning to attract attention as promising means of dealing with the complexity of modern VLSI technology. In this article, we present our views on why asynchronous systems matter. We then present details of our high level synthesis tool SHILPA that can automatically synthesize asynchronous circuits from descriptions in our concurrent programming language,hopCP. We outline many of the novel features of hopCP and also sketch how these constructs are compiled into asynchronous circuits, and then focus on the high level optimizations employed by SHILPA, includingconcurrent guard evaluation and concurrent process decomposition.
    Type of Medium: Electronic Resource
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