Abstract
In this paper a joint implementation of a parity preserving multi-input signature analyzer (PMISA) and a parity checker is described. The PMISA simultaneously can be used for concurrent checking and for testing of digital circuits. In the case of concurrent checking errors are detected by their erroneous parity. If a circuit is tested errors are detected either by their erroneous parity or by the erroneous signature of the PMISA. A possible scan-mode of the PMISA allows its application in a scan path with parity-encoded inputs and outputs of the combinational modules which are driven by register sets. In normal operation mode all the registers of the PMISA can be utilized as functional registers of the combinational circuit.
Similar content being viewed by others
References
R.M. Sedmak, “Design for Self-Verification. An Approach for Dealing with Testability Problems in VLSI-Based Design,”Proc. Int. Test Conf., 1979, pp. 112–120.
E. Fujiwara, N. Muto, and K. Matsuoka, “A Self-Testing Group Parity Prediction Checker and Its Use for Built-in-Testing,”IEEE Trans. Comp., Vol. C-33, No. 6, pp. 578–583, June 1984.
T.R.N. Rao and E. Fujiwara, “Error Control Coding for Computer Systems,” Prentice Hall, New York, 1989.
E.S. Sogomonyan, “Reliability of Self-Testing Using Functional Diagnostic Tools,”Automation and Remote Control, Vol. 49, No. 10, pp. 1376–1380, 1988.
E.S. Sogomonyan and M. Goessel, “Self-Testing and Self-Checking Combinational Circuits with Weakly Independent Outputs,”Proc. 10th IEEE VLSI Test Symposium, Atlantic City, 1992, pp. 298–303.
E.S. Sogomonyan and M. Goessel, “Design of Self-Testing and On-Line Fault Detection Combinational Circuits with Weakly Independent Outputs,”Journal of Electronic Testing: Theory and Applications, Vol. 4, pp. 267–281, 1993.
M. Nicolaidis, “A Unified Built-in-Self-Test Scheme: UBIST,”Proc. 18th Intern. Fault-Tolerant Computing Symposium, 1988, pp. 157–163.
M. Nicolaidis, “Self-Exercising Checkers for Unified Built-in Self-Test (UBIST),”IEEE Trans. on Comput.-Aided Des., Vol. 8, No. 3, pp. 203–218, March 1989.
S.K. Gupta and D.K. Pradhan, “Can Concurrent Checkers Help BIST?,”Proc. Int. Test Conf., 1992, pp. 140–150.
S.K. Gupta and D.K. Pradhan, “Utilization of Concurrent Checkers During Built-in Self-Test,”IEEE Transactions on Computers, January 1996.
E.S. Sogomonyan and M. Goessel, “A New Parity-Preserving Muti-Input Signature Analyzer,”Proc. 1st IEEE Int. On-Line Testing Workshop, Nice, France, 1995, pp. 211–215.
D.K. Pradhan, M.Y. Hsiao, A.M. Patel, and S.Y. Su, “Shift Registers Digned for On-Line Fault Detection,”Proc. 1978 Int'l Symposium Fault Tolerant Computing, Toulouse, June 1978, pp. 173–78.
M.Y. Hsiao, A.M. Patel, and D.K. Pradhan, “Storage Address Generator with On-Line Fault-Detection Capability,”IEEE Trans. Computers, Vol. C-26, No. 11, pp. 1144–1147, 1977.
K. Kim, D.S. Ha, and J.G. Tront, “On Using Signature Registers as Pseudorandom Pattern Generators in Built-in Self-Testing,”IEEE Trans. on Comput.-Aided Des., Vol. 7, No. 8, pp. 919–928, August 1988.
M. Goessel and E.S. Sogomonyan, “Code Disjoint Self-Parity Combinational Circuit for Self-Testing, Concurrent Fault Detection and Parity Scan Design,”Proceedings 12th IEEE VLSI Test Symposium, 1994, pp. 151–157.
B. Koenemann, J. Mucha, and G. Zwiehoff, “Built-in Logic Block Observation Techniques,”Proc. Int. Test Conf., 1979, pp. 37–41.
J.L. Avra and E.J. McCluskey, “Synthesizing for Scan Dependence in Built-in Self-Testable Designs,”Proc. Int. Test Conf., 1993, pp. 734–743.
A. Krasniewski and S. Pilarski, “Circular Self-Test Path: A Low-Cost BIST Technique for VLSI Circuits,”IEEE Trans. on Comput.-Aided Des., Vol. 8, No. 1, pp. 46–55, January 1989.
A.E. Sogomonyan, “Concurrent Error-Detection Circuit Evaluation,”Proceed. of Max-Planck-Society, University of Potsdam, MPI-I-94-605, September 1994, pp. 1–15.
R.K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A.R. Wang, “MIS: A Multi-Level Logic Optimisation System,”IEEE Transactions on Computer-Aided Design, Vol. 6, pp. 1062–1081, November 1987.
H. Fujiwara and A. Yamamoto, “Parity-Scan Design to Reduce the Cost of Test Application,”Proc. Int. Test Conf., 1992, pp. 283–292.
W. Kunz and P. Menon, “Multi-Level Logic Optimization by Implication Analysis,”Proc. IEEE/ACM Int. Conf. on Computer Aided Design, November 1994, pp. 6–13.
G.P. Aksenova, “On Conditions of the Designing of Self-Checking Parity Checkers,”Automation and Remote Control, Vol. 40, No. 9, pp. 1203–1208, 1979.
N.K. Jha and J.A. Abraham, “The Design of Totally Self-Checking Embedded Checkers,”Proc. 14th Intern. Fault-Tolerant Computing Symposium, 1984, pp. 265–270.
Author information
Authors and Affiliations
Rights and permissions
About this article
Cite this article
Goessel, M., Sogomonyan, E.S. A parity-preserving multi-input signature analyzer and its application for concurrent checking and BIST. J Electron Test 8, 165–177 (1996). https://doi.org/10.1007/BF02341822
Received:
Revised:
Issue Date:
DOI: https://doi.org/10.1007/BF02341822