Abstract
Effective parameter extraction is a crucial step in accurate simulation of microelectronic circuits and systems. A parameter extraction program, which is based on a global optimization algorithm, uses a single objective function that minimizes the drain current error between the predicted and measured data. Parameter sets extracted on this basis are adequate for the purpose of digital circuit simulation, but fall short of simulation requirements for analog circuits. The use of a multiple-objective function is proposed, which simultaneously optimizes several critical electrical quantities including the drain current, output conductance, and transconductance. Experimental results with the multiple-objective function are presented, to show the improvement in extracted parameters. The recently developed BSIM_plus MOS transistor model for sub-half-micron integrated circuits uses a compact set of parameters, which greatly enhances the ability to accurately extract parameter values. This model was implemented into the parameter extraction program and some extraction results are presented. The parameter space has several local minima within which a gradient descent method may be trapped. Simulated annealing techniques can be applied to find near-optimal solutions of problems containing multiple local minima in their solution spaces. Experimental results showing the optimization of drain current error using simulation annealing techniques are presented.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
M.I. Elmasry, “Preface,” inDigital MOS Integrated Circuits with Applications to Processors and Memory Design, vol. 2, (M.I. Elmasry, ed.), IEEE Press: Piscataway, NJ, p. xi, 1992.
D. Bursky, “Process advancements fuel IC developments,”Electron. Design, vol. 40, no. 1, p. 37, 1992.
L.G. Kang, Y.T. Kang, B.H. Roh, S.P. Kim, Y.W. Ha, K.M. Hang, and C.-G. Hwang, “New transistor structure optimization for 0.25-µm CMOS technology,” inTech. Digest IEEE/JSAP Symp. on VLSI Technology, 1991, pp. 85–86, Osio, Japan.
A. Nitayama, H. Takato, N. Okabe, K. Sunouchi, K. Hieda, F. Horiguchi, and F. Masuoka, “Multi-pillar surrounding gate transistor for compact and high-speed circuits,”IEEE Trans. Electron Devices, vol. 38, no. 3, pp. 579–583, 1991.
J. Turner, “The half-micron apocalypse,” inHigh-Speed Digital IC Technologies (M. Rocchi, ed.), Artech House: Norwood, MA, pp. 527–542, 1990.
Y. Oowaki, K. Tsuchida, Y. Watanabe, D. Takashima, H. Nakano, S. Watanabe, A. Nitayama, F. Horiguchi, K. Ohuchi, and F. Masuoka,” A 33-ns 64-Mb DRAM,”IEEE J. Solid-State Circuits, vol. 26, no. 11, pp. 1498–1505, 1991.
M. Toyokura, K. Okamoto, H. Kodama, A. Ohtani, T. Araki, and K. Aono, “A video digital signal processor with a vectorpipeline architecture,” inTech. Digest IEEE Int. Solid-State Circuits Conf., San Francisco, CA, pp. 72–73, 1992.
D. Dobberpuhl, R. Witek, R. Allmon, R. Anglin, S. Britton, L. Chao, R. Conrad, D. Dever, B. Gieseke, G. Hoeppner, J. Kowaleski, K. Kuchler, M. Ladd, M. Leary, L. Madden, E. McLellan, D. Meyer, J. Montanaro, D. Priore, V. Rajagopalan, S. Samudrala, and S. Santhanam, “A 200-MHz 64-bit dual-issue microprocessor,” inTech. Digest IEEE Int. Solid-State Circuits Conf., San Francisco, CA, pp. 106–107, 1992.
B.J. Sheu, C.-P. Wan, C.-C. Shih, W.-J. Hsu, and M.C. Hsu, “Determination of process-dependent critical SPICE parameters for application-specific ICs,” inProc. IEEE Int. Conf. Microelectronic Test Structures, Long Beach, CA, pp. 73–78, 1988.
K. Doganis and R.W. Dutton,SUXES-Stanford University Extractor of Model Parameters (User's Manual), Tech. Report, Stanford Electronics Lab., Stanford University, 1982.
M.-C. Jeng, B.J. Sheu, and P.K. Ko,BSIM Parameter Extraction—Algorithms and User's Guide, Memo ERL-M85/79, Electronics Res. Lab., Univ. of California, Berkeley, 1985.
M.R. Garey and D.S. Johnson,Computers and Intractability: A Guide to the Theory of NP-Completeness, Freeman: San Francisco, 1979.
P.J.M. van Laarhoven and E.H.L. Aarts,Simulated Annealing: Theory and Applications, Kluwer: Norwell, MA, 1987.
R.A. Rutenbar, “Simulated annealing algorithms: an overview,”IEEE Circuits Dev. Mag., vol. 5, no. 1, pp. 19–26, 1989.
S.M. Gowda,BSIM_plus: An Advanced MOS Transistor Model for VLSI Circuits, Ph.D. dissertation, University of Southern California, 1992.
B.J. Sheu, D.L. Scharfetter, P.K. Ko, and M.-C. Jeng, “BSIM: Berkeley short-channel IGFET model for MOS transistors,”IEEE J. Solid-State Circuits, vol. 22, no. 4, pp. 558–566, 1987.
K. Doganis and D.L. Scharfetter, “General optimization and extraction of IC device model parameters,”IEEE Trans. Electron Devices, vol. 30, no. 9, pp. 1219–1228, 1983.
A. Vladimirescu and S. Liu,The Simulation of MOS Integrated Circuits Using SPICE2, ERL-M80/7 Memo, Electronics Res. Lab., University of California, Berkeley, 1980.
S.M. Gowda, B.J. Sheu, and C.-H. Chang, “Advanced VLSI circuit simulation using the BSIM_plus model,” inIEEE Custom Integrated Circuits Conf., San Diego, CA, pp. 14.3.1-14.3.4, 1993.
S.M. Gowda and B.J. Sheu, “Explicit geometry dependence of MOS transistor parameters by the pseudo-boundary method,”J. Analog Integrated Circuits Signal Process., vol. 2, no. 2, pp. 105–115, 1992.
S. Kirkpatrick, C.D. Gelatt, Jr., and M.P. Vecchi, “Optimization by simulated annealing,”Science, vol. 220, no. 4598, pp. 671–680, 1983.
M.K. Vai and M.F.D. Ng, “A technology-independent device modeling program using simulated annealing optimization,” inProc. IEEE Custom Integrated Circuits Conf., pp. 9.4.1-9.4.4, 1989.
T. Sakurai, M. Ichida, and A.R. Newton, “Fast simulated diffusion: an optimization algorithm for multi-minimum problems and its application to MOSFET model parameter extraction,” inProc. IEEE Custom Integrated Circuits Conf., San Diego, CA, pp. 8.8.1-8.8.4, 1991.
B.J. Sheu,MOS transistor modeling and characterization for circuit simulation, ERL-M85/22 Memo, Electronic Res. Lab., Univ. of California, Berkeley, 1985.
Author information
Authors and Affiliations
Rights and permissions
About this article
Cite this article
Gowda, S.M., Sheu, B.J. & Chang, R.C.H. Effective parameter extraction using multiple-objective function for VLSI circuits. Analog Integr Circ Sig Process 5, 121–133 (1994). https://doi.org/10.1007/BF01272647
Received:
Revised:
Issue Date:
DOI: https://doi.org/10.1007/BF01272647