ALBERT

Description: A critical PECL (positive emitter-coupled logic) interface to Xilinx interface needed to be changed on an existing flight board. The new Xilinx input interface used a CMOS (complementary metal-oxide semiconductor) type of input, and the driver could meet its thresholds typically, but not in worst-case, according to the data sheet. The previous interface had been based on comparison with an external reference, but the CMOS input is based on comparison with an internal divider from the power supply. A way to measure what the exact input threshold was for this device for 64 inputs on a flight board was needed. The measurement technique allowed an accurate measurement of the voltage required to switch a Xilinx input from high to low for each of the 64 lines, while only probing two of them. Directly driving an external voltage was considered too risky, and tests done on any other unit could not be used to qualify the flight board. The two lines directly probed gave an absolute voltage threshold calibration, while data collected on the remaining 62 lines without probing gave relative measurements that could be used to identify any outliers. The PECL interface was forced to a long-period square wave by driving a saturated square wave into the ADC (analog to digital converter). The active pull-down circuit was turned off, causing each line to rise rapidly and fall slowly according to the input s weak pull-down circuitry. The fall time shows up as a change in the pulse width of the signal ready by the Xilinx. This change in pulse width is a function of capacitance, pulldown current, and input threshold. Capacitance was known from the different trace lengths, plus a gate input capacitance, which is the same for all inputs. The pull-down current is the same for all inputs including the two that are probed directly. The data was combined, and the Excel solver tool was used to find input thresholds for the 62 lines. This was repeated over different supply voltages and temperatures to show that the interface had voltage margin under all worst case conditions. Gate input thresholds are normally measured at the manufacturer when the device is on a chip tester. A key function of this machine was duplicated on an existing flight board with no modifications to the nets to be tested, with the exception of changes in the FPGA program.

Description: Data is communicated between redundant channels formatted in blocks having an initial command word followed by a destination code, starting address and a variable number of data words including a word count. The blocks are transmitted between each channel and all of the channels over cross-channel data links, each channel receiving the data blocks and determining the validity thereof by counting the number of data words received and comparing that number to the word count transmitted for that block. An interrupt signal indicative of invalidity of a block is provided in the event of a miscompare. A stop address is generated for each block received for storage at the start address. A memory address is generated for each valid word received for storage in sequence starting immediately after the start address. The next block received has its start address placed immediately at the end of the previously received block.

Description: An adaptive algorithm implemented in digital or analog form is used in conjunction with a voltage controlled amplifier to compensate for the feedthrough capacitance of piezoelectric sensoriactuator. The mechanical response of the piezoelectric sensoriactuator is resolved from the electrical response by adaptively altering the gain imposed on the electrical circuit used for compensation. For wideband, stochastic input disturbances, the feedthrough capacitance of the sensoriactuator can be identified on-line, providing a means of implementing direct-rate-feedback control in analog hardware. The device is capable of on-line system health monitoring since a quasi-stable dynamic capacitance is indicative of sustained health of the piezoelectric element.