Electronic Resource
[S.l.]
:
American Institute of Physics (AIP)
Journal of Applied Physics
87 (2000), S. 1543-1549
ISSN:
1089-7550
Source:
AIP Digital Archive
Topics:
Physics
Notes:
Under gravitational and thermal constraints of integrated-circuit (IC) process technology, 300-mm-diam silicon wafers can deform via slip dislocation generation and propagation, degrading the electrical characteristics of the leading edge device. We present a force balance model to describe the strain relaxation in large wafer diameter, which includes heat transfer effects and the upper yield point of the silicon material. The material attributes, such as oxygen content and the state of oxygen aggregation, are taken into account. The theoretical approach allows the calculation of wafer mechanics and ramp rate profiles for an arbitrary high-temperature process. Plastic deformation of silicon wafers caused by thermal stresses at high temperatures can be controlled by process design. Deformation due to gravitational forces can be prevented through appropriate equipment design. The quantitative theory proposed here provides guidance for computer simulation to configure stable slip-free wafer process flow under mechanical and thermal loads. Applications include high speed simulation of "what if?" experiments, and initial simulations of large scale experimental sequences. The simulator developed can also be used by IC manufacturers to determine optimum wafer throughput and cycle times in front-end device processes. © 2000 American Institute of Physics.
Type of Medium:
Electronic Resource
URL:
http://dx.doi.org/10.1063/1.372047
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