ALBERT

Notes: The rapid adoption of damascene copper processing has brought about an increased need to understand and control microstructure in the barrier, seed and electroplated copper layers during manufacture. We will discuss an in-line, x-ray diffraction based metrology for rapidly characterizing thin film polycrystalline microstructures on 300 mm silicon wafers in terms of crystallographic texture, phase composition, and film thickness. The microstructure control plays an increasingly important role in improving the performance and reliability of ULSI devices that use the damascene copper technology at 0.13-µm node and below. The problems related to delamination, stress voiding, and electromigration failures could be mitigated by the selection of proper materials, processing methods, and manufacturing tools. The optimum process would result in a tailored microstructure of barrier/seed/electroplated copper aggregate. At the same time, the microstructure could be used as an internal sensor, sensitive to process excursions and providing guidance for the corrective actions. The texture and crystallographic phase data can be used as a direct measure of the deposition process in terms of film quality, reproducibility, and stability over time. The spatial distribution of crystallographic texture and phase can be measured on a single wafer in order to check wafer uniformity. More importantly, the same measurements can be carried out at predetermined intervals on wafers from a single deposition tool, and the results used to create a database that can be applied to trend charting and tool qualification. Examples of microstructure control in damascene copper processing include: process development and qualification, process control and stability, deposition tool qualification, and on-line R&D. Examples of texture control will refer to materials andprocesses typical of damascene copper technology for ULSI. A typical processing route includes the PVD deposition of a barrier layer and copper seed layer, followed by copper electroplate (EP), anneal, and chemical-mechanical planarization (CMP). All the processing steps affect the texture of annealed copper, and therefore affect directly the performance of interconnects

Notes: The ability to control the crystallographic orientation of both the seed layer and the electroplated copper grains is important in obtaining highly reliable Cu interconnects for ultra-large scale integration (ULSI) circuitry. One of the factors controlling film texture is the roughness of the deposition surface. In this paper the effects of dielectric roughness on the crystallographic texture of physical vapor deposited (PVD) copper seed layers and, subsequently, on the texture of electroplated (EP) copper have been investigated. Six relevant interlevel dielectric materials were examined: tetraethyloorthosilicate (TEOS), borophosphosilicate glass (BPSG), silane oxide, silicon nitride, SiLKTM (from the Dow Chemical Corporation), and polysilicon were deposited on 200 mm (001) Si wafers. The RMS surface roughness of these dielectric layers, measured by AFM, ranged from 0.32 nm to 20.51 nm. Texture was analyzed on a dedicated x-ray diffractometer equipped with a two dimensional detector collecting incomplete pole figures with a 1.0 degree resolution in pole figure space. The orientation distribution functions (ODF) were calculated using the arbitrary defined cells method and the volume fractions of major fiber texture components were derived from the ODF. The predominant texture components of the PVD and EP copper were (111) and (511) fiber. It was found that the volume fraction of (111) fiber decreased as the dielectric surface roughness increased. One exception was with the SiLKTM dielectric, which produced significantly weaker texture than other dielectrics with similar surface roughness. The copper films deposited on polysilicon, which possessed the roughest deposition surface of all the dielectric films had a randomtexture. Finally, a mixture of strong (111) and (511) fiber textures of EP copper was achieved on dielectric underlayers with smoother surfaces. The results demonstrate that the deposition surface roughness plays an important role in establishing the texture in overlying PVD and EP Cu films. The texture of PVD and EP copper may serve as a useful indicator of the underlayer roughness

Notes: We present the principles of operation and a summary of results from in-fab automated X-ray diffraction (XRD) metrology in support of copper damascene roduction. The automated XRD tools (an example is shown in Figure 1) are capable of rapid mapping of 300 mm wafers (with a throughput rate of 40 wafers/hour) of quantitative information about the film crystallographic composition, texture and thickness with a spatial resolution down to 30 microns. Microstructure control plays an increasingly important role in improving the performance and reliability of ULSI devices that use the damascene copper technology at 130 nm node and below. The problems related to delamination, stress voiding, and electromigration failures could be mitigated by the selection of proper materials, processing methods, and manufacturing tools. The optimum process would result in a tailored microstructure of barrier/seed/electroplated copper aggregate. At the same time, the microstructure could be used as an internal sensor, sensitive to process excursions and providing guidance for corrective actions. The texture and crystallographic phase data can be used as a direct measure of the deposition process in terms of film quality, reproducibility, and stability over time. The spatial distribution of crystallographic texture and phase can be measured on a single wafer in order to check wafer uniformity. More importantly, the same measurements can be carried out at predetermined intervals on wafers from a single deposition tool, and the results used to create a database that can be applied to trend charting and tool qualification. Examples of microstructure control in damascene copper processing include: process development and qualification, process control and stability, process excursion and post maintenance stability, deposition tool qualification, and on-line R&D. The examples of texture control will refer to materials and processes typical of damascene copper technology for ULSI. A typical processing route includes the PVD deposition of a barrier layer and copper seed layer, followed by copper electroplate, anneal and chemical- mechanical planarization. All the processing steps affect the texture of annealed copper, and therefore affect directly the performance of interconnects. We will also present examples of application to processing of metal gates (NiSi films) and ferroelectric non-volatile memory (PZT films)