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    Off-Line Testing for Bridge Faults in CMOS Domino Logic Circuits (1997)
    In:  CASI
    Details
    Publication Date: 2019-08-16
    Description: Bridge faults, especially in CMOS circuits, have unique characteristics which make them difficult to detect during testing. This paper presents a technique for detecting bridge faults which have an effect on the output of CMOS Domino logic circuits. The faults are modeled at the transistor level and this technique is based on analyzing the off-set of the function during off-line testing.
    Keywords: Computer Programming and Software
    Type: URC97020 , NASA University Research Centers Technical Advances in Education, Aeronautics, Space, Autonomy, Earth and Environment; 1; 115-120
    Format: application/pdf
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