Publication Date:
2019-07-13
Description:
Within the field of computer software, simulation and verification are complementary processes. Simulation methods can be used to verify software by performing variable range analysis. More general verification procedures, such as those described in this paper, can be implicitly, viewed as attempts at modeling the end-product software. From software requirement methodology, each component of the verification system has some element of simulation to it. Conversely, general verification procedures can be used to analyze simulation software. A dynamic analyzer is described which can be used to obtain properly scaled variables for an analog simulation, which is first digitally simulated. In a similar way, it is thought that the other system components and indeed the whole system itself have the potential of being effectively used in a simulation environment.
Keywords:
COMPUTER PROGRAMMING AND SOFTWARE
Type:
Summer Computer Simulation Conference; Jul 12, 1976 - Jul 14, 1976; Washington, DC
Format:
text
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